[PATCH] Fix powerpc bootstrap when using --enable-checking=rtl

[Peter Bergner]

This patch fixes the bootstrap problem on powerpc that Andreas ran into
using --enable-checking=rtl.  The problem was that adjacent_mem_locations
wasn't setup to handle store instructions embedded inside a parallel.
However, store with update insns contain stores embedded in parallels,
so the solution here is to reach inside the parallel for the actual
store.

The passed bootstrap (with and without --enable-checking=rtl) and
regtesting on powerpc64-linux.  Is this ok for mainline?  This problem
also exists on 4.2, should we fix it there too?

I'll note that I'm heading on vacation for a week tomorrow (Saturday),
so if this patch is ok, either someone can check it in for me, or I'll
check it in when I get back.

Peter


2006-11-10  Peter Bergner  <bergner@vnet.ibm.com>

	* config/rs6000/rs6000.c (get_store_dest): New.
	(adjacent_mem_locations): Use get_store_dest() to get
	the rtl of the store destination.

Index: config/rs6000/rs6000.c
===================================================================
--- config/rs6000/rs6000.c	(revision 118684)
+++ config/rs6000/rs6000.c	(working copy)
@@ -674,6 +674,7 @@
 static bool is_cracked_insn (rtx);
 static bool is_branch_slot_insn (rtx);
 static bool is_load_insn (rtx);
+static rtx get_store_dest (rtx pat);
 static bool is_store_insn (rtx);
 static bool set_to_load_agen (rtx,rtx);
 static bool adjacent_mem_locations (rtx,rtx); 
@@ -17004,9 +17005,9 @@
 adjacent_mem_locations (rtx insn1, rtx insn2)
 {
 
-  rtx a = SET_DEST (PATTERN (insn1));
-  rtx b = SET_DEST (PATTERN (insn2));
- 
+  rtx a = get_store_dest (PATTERN (insn1));
+  rtx b = get_store_dest (PATTERN (insn2));
+
   if ((GET_CODE (XEXP (a, 0)) == REG
        || (GET_CODE (XEXP (a, 0)) == PLUS
 	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
@@ -17260,6 +17261,28 @@
   return is_store_insn1 (PATTERN (insn));
 }
 
+/* Return the dest of a store insn.  */
+
+static rtx
+get_store_dest (rtx pat)
+{
+  gcc_assert (is_store_insn1 (pat));
+
+  if (GET_CODE (pat) == SET)
+    return SET_DEST (pat);
+  else if (GET_CODE (pat) == PARALLEL)
+    {
+      int i;
+
+      for (i = 0; i < XVECLEN (pat, 0); i++)
+	if (is_store_insn1 (XVECEXP (pat, 0, i)))
+	  return XVECEXP (pat, 0, i);
+    }
+  /* We shouldn't get here, because we should have either a simple
+     store insn or a store with update which are covered above.  */
+  gcc_assert (0);
+}
+
 /* Returns whether the dependence between INSN and NEXT is considered
    costly by the given target.  */