MIPS patches for Broadcom SB-1A
James E Wilson
wilson@specifix.com
Mon Jun 26 20:54:00 GMT 2006
This adds support for a new Broadcom processor, the MIPS SB-1A. The
SB-1A has only one small difference from the SB-1. On the SB-1, simple
alu instructions can be executed on either a load/store unit or the alu
unit. On the SB-1A, they can only be executed on the alu units. This
makes the processor much easier to schedule for.
Mostly this patch is cloning the existing SB-1 support, while trying to
keep the non-scheduler changes as simple as possible. The only real
change is that a few patterns in the sb1.md file are different for the
SB-1 and SB-1A.
I will wait for comments before checking in the patch.
--
Jim Wilson, GNU Tools Support, http://www.specifix.com
-------------- next part --------------
2006-06-24 James E Wilson <wilson@specifix.com>
* config/mips/mips.md (cpu): Add sb1a.
* config/mips/sb1.md: Modify almost all patterns to accept sb1a in
addition to sb1. Adjust comments to clarify SB-1A differences from
SB-1.
(ir_sb1a_load): New. Modify bypasses to use it.
(ir_sb1a_simple_alu): Likewise.
* config/mips/mips.c (mips_cpu_info_table): Add sb1a.
(mips_rtx_cost_data): Add PROCESSOR_SB1A support.
(mips_issue_rate): Add PROCESSOR_SB1A.
(mips_multipass_dfa_lookahead): Use TUNE_SB1 instead of PROCESSOR_SB1.
* config/mips/mips.h (processor_type): Add PROCESSOR_SB1A.
(TARGET_SB1): Add PROCESSOR_SB1A check.
(TUNE_SB1): Likewise.
Index: mips.md
===================================================================
--- mips.md (revision 114960)
+++ mips.md (working copy)
@@ -340,7 +340,7 @@ (define_attr "length" ""
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
- "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
+ "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
Index: sb1.md
===================================================================
--- sb1.md (revision 114960)
+++ sb1.md (working copy)
@@ -90,7 +90,7 @@ (define_attr "sb1_fp_pipes" "one,two"
;;
(define_insn_reservation "ir_sb1_unknown" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "unknown,multi"))
"sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1")
@@ -102,15 +102,16 @@ (define_insn_reservation "ir_sb1_unknown
;; investigated. Maybe using 2 here will give better results.
(define_insn_reservation "ir_sb1_branch" 0
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "branch,jump,call"))
"sb1_ex0")
;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data
;; register as destination.
-;; ??? Can co-issue a load with a dependent arith insn if it executes on an EX
-;; unit. Can not co-issue if the dependent insn executes on an LS unit.
+;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on
+;; an EX unit. Can not co-issue if the dependent insn executes on an LS unit.
+;; SB-1A can always co-issue here.
;; A load normally has a latency of zero cycles. In some cases, dependent
;; insns can be issued in the same cycle. However, a value of 1 gives
@@ -121,17 +122,22 @@ (define_insn_reservation "ir_sb1_load" 1
(eq_attr "type" "load,prefetch"))
"sb1_ls0 | sb1_ls1")
+(define_insn_reservation "ir_sb1a_load" 0
+ (and (eq_attr "cpu" "sb1a")
+ (eq_attr "type" "load,prefetch"))
+ "sb1_ls0 | sb1_ls1")
+
;; Can not co-issue fpload with fp exe when in 32-bit mode.
(define_insn_reservation "ir_sb1_fpload" 0
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fpload")
(ne (symbol_ref "TARGET_FLOAT64")
(const_int 0))))
"sb1_ls0 | sb1_ls1")
(define_insn_reservation "ir_sb1_fpload_32bitfp" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fpload")
(eq (symbol_ref "TARGET_FLOAT64")
(const_int 0))))
@@ -140,14 +146,14 @@ (define_insn_reservation "ir_sb1_fpload_
;; Indexed loads can only execute on LS1 pipe.
(define_insn_reservation "ir_sb1_fpidxload" 0
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fpidxload")
(ne (symbol_ref "TARGET_FLOAT64")
(const_int 0))))
"sb1_ls1")
(define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fpidxload")
(eq (symbol_ref "TARGET_FLOAT64")
(const_int 0))))
@@ -156,7 +162,7 @@ (define_insn_reservation "ir_sb1_fpidxlo
;; prefx can only execute on the ls1 pipe.
(define_insn_reservation "ir_sb1_prefetchx" 0
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "prefetchx"))
"sb1_ls1")
@@ -164,19 +170,19 @@ (define_insn_reservation "ir_sb1_prefetc
;; there is a RAW dependency.
(define_insn_reservation "ir_sb1_store" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "store"))
"sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0")
(define_insn_reservation "ir_sb1_fpstore" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "fpstore"))
"sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
;; Indexed stores can only execute on LS1 pipe.
(define_insn_reservation "ir_sb1_fpidxstore" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "fpidxstore"))
"sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
@@ -188,18 +194,18 @@ (define_insn_reservation "ir_sb1_fpidxst
;; be an address dependence.
(define_bypass 3
- "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
- ir_sb1_fpidxload_32bitfp"
- "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
- ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
+ "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
+ ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
+ "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
+ ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
(define_bypass 3
- "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
- ir_sb1_fpidxload_32bitfp"
+ "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
+ ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
"ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
"store_data_bypass_p")
-;; Simple alu instructions can execute on the LS1 unit.
+;; On SB-1, simple alu instructions can execute on the LS1 unit.
;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX
;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to
@@ -233,18 +239,26 @@ (define_insn_reservation "ir_sb1_simple_
(eq_attr "type" "const,arith"))
"sb1_ls1 | sb1_ex1 | sb1_ex0")
+;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we
+;; have none of the above problems.
+
+(define_insn_reservation "ir_sb1a_simple_alu" 1
+ (and (eq_attr "cpu" "sb1a")
+ (eq_attr "type" "const,arith"))
+ "sb1_ex1 | sb1_ex0")
+
;; ??? condmove also includes some FP instructions that execute on the FP
;; units. This needs to be clarified.
(define_insn_reservation "ir_sb1_alu" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "condmove,nop,shift"))
"sb1_ex1 | sb1_ex0")
;; These are type arith/darith that only execute on the EX0 unit.
(define_insn_reservation "ir_sb1_alu_0" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "slt,clz,trap"))
"sb1_ex0")
@@ -255,25 +269,25 @@ (define_insn_reservation "ir_sb1_alu_0"
;; be an address dependence.
(define_bypass 5
- "ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
- "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
- ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
+ "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
+ "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
+ ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
(define_bypass 5
- "ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
+ "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
"ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
"store_data_bypass_p")
;; mf{hi,lo} is 1 cycle.
(define_insn_reservation "ir_sb1_mfhi" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "mfhilo")
(not (match_operand 1 "lo_operand"))))
"sb1_ex1")
(define_insn_reservation "ir_sb1_mflo" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "mfhilo")
(match_operand 1 "lo_operand")))
"sb1_ex1")
@@ -281,7 +295,7 @@ (define_insn_reservation "ir_sb1_mflo" 1
;; mt{hi,lo} to mul/div is 4 cycles.
(define_insn_reservation "ir_sb1_mthilo" 4
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "mthilo"))
"sb1_ex1")
@@ -295,7 +309,7 @@ (define_bypass 3 "ir_sb1_mthilo" "ir_sb1
;; to/from hilo registers.
(define_insn_reservation "ir_sb1_mulsi" 3
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"sb1_ex1+sb1_mul")
@@ -304,7 +318,7 @@ (define_insn_reservation "ir_sb1_mulsi"
;; Blocks any other multiply insn issue for 1 cycle.
(define_insn_reservation "ir_sb1_muldi" 4
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"sb1_ex1+sb1_mul, sb1_mul")
@@ -320,8 +334,8 @@ (define_bypass 3 "ir_sb1_muldi" "ir_sb1_
(define_bypass 7
"ir_sb1_mulsi,ir_sb1_muldi"
- "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
- ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
+ "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
+ ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
(define_bypass 7
"ir_sb1_mulsi,ir_sb1_muldi"
@@ -340,37 +354,37 @@ (define_bypass 7
;; stall for 33 cycles. This does not seem significant enough to worry about.
(define_insn_reservation "ir_sb1_divsi" 36
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "SI")))
"sb1_ex1, nothing*3, sb1_div*32")
(define_insn_reservation "ir_sb1_divdi" 68
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI")))
"sb1_ex1, nothing*3, sb1_div*64")
(define_insn_reservation "ir_sb1_fpu_2pipes" 4
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
(eq_attr "sb1_fp_pipes" "two")))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_fpu_1pipe" 4
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
(eq_attr "sb1_fp_pipes" "one")))
"sb1_fp1")
(define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frdiv2,frsqrt2")
(eq_attr "sb1_fp_pipes" "two")))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frdiv2,frsqrt2")
(eq_attr "sb1_fp_pipes" "one")))
"sb1_fp1")
@@ -381,26 +395,26 @@ (define_insn_reservation "ir_sb1_fpu_ste
;; ??? Blocks issue of another non-madd/msub after 4 cycles.
(define_insn_reservation "ir_sb1_fmadd_2pipes" 8
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fmadd")
(eq_attr "sb1_fp_pipes" "two")))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_fmadd_1pipe" 8
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fmadd")
(eq_attr "sb1_fp_pipes" "one")))
"sb1_fp1")
(define_insn_reservation "ir_sb1_fcmp" 4
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(eq_attr "type" "fcmp"))
"sb1_fp1")
;; mtc1 latency 5 cycles.
(define_insn_reservation "ir_sb1_mtxfer" 5
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "xfer")
(match_operand 0 "fpr_operand")))
"sb1_fp0")
@@ -408,7 +422,7 @@ (define_insn_reservation "ir_sb1_mtxfer"
;; mfc1 latency 1 cycle.
(define_insn_reservation "ir_sb1_mfxfer" 1
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "xfer")
(not (match_operand 0 "fpr_operand"))))
"sb1_fp0")
@@ -417,14 +431,14 @@ (define_insn_reservation "ir_sb1_mfxfer"
;; restrictions.
(define_insn_reservation "ir_sb1_divsf_2pipes" 24
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fdiv")
(and (eq_attr "mode" "SF")
(eq_attr "sb1_fp_pipes" "two"))))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_divsf_1pipe" 24
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fdiv")
(and (eq_attr "mode" "SF")
(eq_attr "sb1_fp_pipes" "one"))))
@@ -434,14 +448,14 @@ (define_insn_reservation "ir_sb1_divsf_1
;; restrictions.
(define_insn_reservation "ir_sb1_divdf_2pipes" 32
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fdiv")
(and (eq_attr "mode" "DF")
(eq_attr "sb1_fp_pipes" "two"))))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_divdf_1pipe" 32
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fdiv")
(and (eq_attr "mode" "DF")
(eq_attr "sb1_fp_pipes" "one"))))
@@ -451,14 +465,14 @@ (define_insn_reservation "ir_sb1_divdf_1
;; restrictions.
(define_insn_reservation "ir_sb1_recipsf_2pipes" 12
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frdiv")
(and (eq_attr "mode" "SF")
(eq_attr "sb1_fp_pipes" "two"))))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_recipsf_1pipe" 12
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frdiv")
(and (eq_attr "mode" "SF")
(eq_attr "sb1_fp_pipes" "one"))))
@@ -468,14 +482,14 @@ (define_insn_reservation "ir_sb1_recipsf
;; restrictions.
(define_insn_reservation "ir_sb1_recipdf_2pipes" 20
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frdiv")
(and (eq_attr "mode" "DF")
(eq_attr "sb1_fp_pipes" "two"))))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_recipdf_1pipe" 20
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frdiv")
(and (eq_attr "mode" "DF")
(eq_attr "sb1_fp_pipes" "one"))))
@@ -485,14 +499,14 @@ (define_insn_reservation "ir_sb1_recipdf
;; restrictions.
(define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fsqrt")
(and (eq_attr "mode" "SF")
(eq_attr "sb1_fp_pipes" "two"))))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fsqrt")
(and (eq_attr "mode" "SF")
(eq_attr "sb1_fp_pipes" "one"))))
@@ -502,14 +516,14 @@ (define_insn_reservation "ir_sb1_sqrtsf_
;; restrictions.
(define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fsqrt")
(and (eq_attr "mode" "DF")
(eq_attr "sb1_fp_pipes" "two"))))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "fsqrt")
(and (eq_attr "mode" "DF")
(eq_attr "sb1_fp_pipes" "one"))))
@@ -519,14 +533,14 @@ (define_insn_reservation "ir_sb1_sqrtdf_
;; restrictions.
(define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frsqrt")
(and (eq_attr "mode" "SF")
(eq_attr "sb1_fp_pipes" "two"))))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frsqrt")
(and (eq_attr "mode" "SF")
(eq_attr "sb1_fp_pipes" "one"))))
@@ -536,14 +550,14 @@ (define_insn_reservation "ir_sb1_rsqrtsf
;; restrictions.
(define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frsqrt")
(and (eq_attr "mode" "DF")
(eq_attr "sb1_fp_pipes" "two"))))
"sb1_fp1 | sb1_fp0")
(define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28
- (and (eq_attr "cpu" "sb1")
+ (and (eq_attr "cpu" "sb1,sb1a")
(and (eq_attr "type" "frsqrt")
(and (eq_attr "mode" "DF")
(eq_attr "sb1_fp_pipes" "one"))))
Index: mips.c
===================================================================
--- mips.c (revision 114960)
+++ mips.c (working copy)
@@ -759,6 +759,7 @@ const struct mips_cpu_info mips_cpu_info
{ "5kf", PROCESSOR_5KF, 64 },
{ "20kc", PROCESSOR_20KC, 64 },
{ "sb1", PROCESSOR_SB1, 64 },
+ { "sb1a", PROCESSOR_SB1A, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
/* End marker */
@@ -1016,6 +1017,21 @@ static struct mips_rtx_cost_data const m
4 /* memory_latency */
},
{ /* SB1 */
+ /* These costs are the same as the SB-1A below. */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (4), /* fp_mult_df */
+ COSTS_N_INSNS (24), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (3), /* int_mult_si */
+ COSTS_N_INSNS (4), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* SB1-A */
+ /* These costs are the same as the SB-1 above. */
COSTS_N_INSNS (4), /* fp_add */
COSTS_N_INSNS (4), /* fp_mult_sf */
COSTS_N_INSNS (4), /* fp_mult_df */
@@ -9904,6 +9920,7 @@ mips_issue_rate (void)
return 2;
case PROCESSOR_SB1:
+ case PROCESSOR_SB1A:
/* This is actually 4, but we get better performance if we claim 3.
This is partly because of unwanted speculative code motion with the
larger number, and partly because in most common cases we can't
@@ -9922,7 +9939,7 @@ static int
mips_multipass_dfa_lookahead (void)
{
/* Can schedule up to 4 of the 6 function units in any one cycle. */
- if (mips_tune == PROCESSOR_SB1)
+ if (TUNE_SB1)
return 4;
return 0;
Index: mips.h
===================================================================
--- mips.h (revision 114960)
+++ mips.h (working copy)
@@ -58,6 +58,7 @@ enum processor_type {
PROCESSOR_R8000,
PROCESSOR_R9000,
PROCESSOR_SB1,
+ PROCESSOR_SB1A,
PROCESSOR_SR71000,
PROCESSOR_MAX
};
@@ -208,7 +209,8 @@ extern const struct mips_rtx_cost_data *
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
-#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
+#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
+ || mips_arch == PROCESSOR_SB1A)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
/* Scheduling target defines. */
@@ -223,7 +225,8 @@ extern const struct mips_rtx_cost_data *
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
-#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
+#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
+ || mips_tune == PROCESSOR_SB1A)
/* True if the pre-reload scheduler should try to create chains of
multiply-add or multiply-subtract instructions. For example,
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