[PATCH,M32C]:Mismatch of instruction pattern.

[Naveen H.S.]

Hi DJ,

>> you have to set the flags to "x" instead, so that gcc won't
>> assume it can rely on them 

As per your suggestion, please find attached the following patch 
"gccpatch_m32c.tar.gz".

>> There are some regressions caused by your patch (attached), did you 
>> see these

We have verified that no new regression failures are getting added with
our patch. The testcase mentioned by you are failing with the fresh 
toolchain as well. The toolchain built after applying our patch 
are also producing the same results as fresh toolchain. 

Also, Please let us know if there should be any further modifications
in the patch.

No new regressions found.

ChangeLog
2006-06-12	Naveen H.S <naveenh@kpitcummins.com>
		Jayant Sonar <jayants@kpitcummins.com>
		Jaydeep Vipradas <jaydeepv@kpitcummins.com>

	* gcc/config/m32c/addsub.md: New instructions for
	add.l, adcf.w, adc.w, sub.l, sbb.w are implemented.
	* gcc/config/m32c/bitops.md: and.w, or.w, xor.w are 
	enhanced for 32 bit operations.
	* gcc/config/m32c/mov.md: A peephole is added to combine
	2 mov.w into a mov.l instruction for storing immediate
	values of a double variable.
      * gcc/config/m32c/m32.c.: A function m32c_immd_dbl_mov
	added to verify the conditions for the peephole and to
	create operands in SImode.
	
Regards,
Naveen H.S.
KPIT Cummins InfoSystems Ltd.
Pune, India
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