[rfc] multi-word subreg lowering pass

[DJ Delorie]

> The approach I'm using is neutral with regard to targets with two
> register sizes.

The m32c would be a good test target, then.  It has six register sizes
- three hard (8, 16, 24 bit), and three more when you include pairings
(another 16, and 32 bit), triplings (48 bit) and quaddings (64 bit)
needed by some opcodes.  Plus there are two 64 bit types with
different quadding orders.

I can't even *use* some of the sizes with gcc the way it is now.