Committed: fix PR target/25947; unrecognizable insn caused by splitter in cris.md
Hans-Peter Nilsson
hans-peter.nilsson@axis.com
Thu Jan 26 03:30:00 GMT 2006
It would be Nice if: 1) '%' as a constraint modifier was active after
reload, 2) define_splits had names, 3) there was a Canonical Order between
reg and mem (with mems last). For the bug, 1 and 3 conspired; see the PR.
Candidate for 4.1 too, using Mark's lenience regarding target maintainer
decisions for non-regression fixes.
Tested cross to cris-axis-elf and cris-axis-linux-gnu.
gcc:
PR target/25947
* config/cris/cris.c (cris_order_for_addsi3): New function.
* config/cris/cris-protos.h: Prototype it.
* config/cris/cris.md (split for "move.S1 [rx=rx+i],ry")
(split for "move.S1 ry,[rx=rx+i]", split for "clear.[bwd] [rx=rx+i]")
(split for "mov(s|u).S1 [rx=rx+i],ry", split for "op.S1 [rx=rx+i],ry")
(split for "op.S1 [rx=rx+i],ry (swapped)")
(split for "op(s|u).S1 [rx=rx+i],ry")
(split for "op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)"):
Apply cris_order_for_addsi3 when generating addsi3 insns.
gcc/testsuite:
PR target/25947
* gcc.dg/torture/pr25947-1.c: New test.
--- /dev/null 2004-02-23 22:02:56.000000000 +0100
+++ gcc.dg/torture/pr25947-1.c 2006-01-26 01:21:31.667195753 +0100
@@ -0,0 +1,21 @@
+/* PR target/25947: define_split in cris.md caused unrecognized insn. */
+/* { dg-options "-fpic" { target fpic } } */
+
+extern char *rl_line_buffer;
+extern int rl_point;
+extern int rl_end;
+static const char *vi_motion = " hl^$0ftFT;,%wbeWBE|";
+void
+rl_vi_complete (int ignore, int key)
+{
+ if ((rl_point < rl_end)
+ &&
+ (!(((rl_line_buffer[rl_point]) == ' ')
+ || ((rl_line_buffer[rl_point]) == '\t'))))
+ {
+ if (!
+ (((rl_line_buffer[rl_point + 1]) == ' ')
+ || ((rl_line_buffer[rl_point + 1]) == '\t')))
+ rl_vi_end_word (1, 'E');
+ }
+}
Index: cris.c
===================================================================
--- cris.c (revision 110173)
+++ cris.c (working copy)
@@ -3257,6 +3257,22 @@ cris_expand_pic_call_address (rtx *opp)
}
}
+/* Make sure operands are in the right order for an addsi3 insn as
+ generated by a define_split. A MEM as the first operand isn't
+ recognized by addsi3 after reload. OPERANDS contains the operands,
+ with the first at OPERANDS[N] and the second at OPERANDS[N+1]. */
+
+void
+cris_order_for_addsi3 (rtx *operands, int n)
+{
+ if (MEM_P (operands[n]))
+ {
+ rtx tem = operands[n];
+ operands[n] = operands[n + 1];
+ operands[n + 1] = tem;
+ }
+}
+
/* Use from within code, from e.g. PRINT_OPERAND and
PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
different things depending on whether code operand or constant is
Index: cris.md
===================================================================
--- cris.md (revision 110173)
+++ cris.md (working copy)
@@ -3285,7 +3285,10 @@ (define_split
|| rtx_equal_p (operands[3], operands[2]))"
[(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (match_dup 4))]
- "operands[4] = replace_equiv_address (operands[5], operands[3]);")
+{
+ operands[4] = replace_equiv_address (operands[5], operands[3]);
+ cris_order_for_addsi3 (operands, 1);
+})
;; move.S1 ry,[rx=rx+rz.S2]
@@ -3325,7 +3328,10 @@ (define_split
|| rtx_equal_p (operands[3], operands[1]))"
[(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
(set (match_dup 5) (match_dup 2))]
- "operands[5] = replace_equiv_address (operands[6], operands[3]);")
+{
+ operands[5] = replace_equiv_address (operands[6], operands[3]);
+ cris_order_for_addsi3 (operands, 0);
+})
;; clear.[bwd] [rx=rx+rz.S2]
@@ -3362,7 +3368,7 @@ (define_split
|| rtx_equal_p (operands[2], operands[1]))"
[(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
(set (mem:BWD (match_dup 2)) (const_int 0))]
- "")
+ "cris_order_for_addsi3 (operands, 0);")
;; mov(s|u).S1 [rx=rx+rz.S2],ry
@@ -3404,7 +3410,10 @@ (define_split
|| rtx_equal_p (operands[2], operands[3]))"
[(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
- "operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);")
+{
+ operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);
+ cris_order_for_addsi3 (operands, 1);
+})
;; op.S1 [rx=rx+i],ry
@@ -3424,7 +3433,10 @@ (define_split
|| rtx_equal_p (operands[4], operands[3]))"
[(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
(set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
- "operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);")
+{
+ operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);
+ cris_order_for_addsi3 (operands, 2);
+})
;; op.S1 [rx=rx+rz.S2],ry
@@ -3492,7 +3504,10 @@ (define_split
|| rtx_equal_p (operands[4], operands[3]))"
[(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
(set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
- "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
+{
+ operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);
+ cris_order_for_addsi3 (operands, 2);
+})
;; op(s|u).S1 [rx=rx+rz.S2],ry
@@ -3543,9 +3558,12 @@ (define_split
|| rtx_equal_p (operands[4], operands[3]))"
[(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
(set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
- "operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
- replace_equiv_address (XEXP (operands[6], 0),
- operands[4]));")
+{
+ operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
+ replace_equiv_address (XEXP (operands[6], 0),
+ operands[4]));
+ cris_order_for_addsi3 (operands, 2);
+})
;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
@@ -3594,9 +3612,12 @@ (define_split
|| rtx_equal_p (operands[4], operands[3]))"
[(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
(set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
- "operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
- replace_equiv_address (XEXP (operands[5], 0),
- operands[4]));")
+{
+ operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
+ replace_equiv_address (XEXP (operands[5], 0),
+ operands[4]));
+ cris_order_for_addsi3 (operands, 2);
+})
;; Splits for addressing prefixes that have no side-effects, so we can
;; fill a delay slot. Never split if we lose something, though.
Index: cris-protos.h
===================================================================
--- cris-protos.h (revision 110173)
+++ cris-protos.h (working copy)
@@ -49,6 +49,7 @@ extern int cris_cfun_uses_pic_table (voi
extern rtx cris_gen_movem_load (rtx, rtx, int);
extern rtx cris_emit_movem_store (rtx, rtx, int, bool);
extern void cris_expand_pic_call_address (rtx *);
+extern void cris_order_for_addsi3 (rtx *, int);
#endif /* RTX_CODE */
extern void cris_asm_output_label_ref (FILE *, char *);
extern void cris_target_asm_named_section (const char *, unsigned int, tree);
brgds, H-P
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