PATCH: IA64 HP-UX bootstrap failure

[Steve Ellcey]

The GCC bootstrap on IA64 HP-UX started failing with SVN version 110852.
That change removed -floop-optimize2 and enabled fmove-loop-invariants
by default.  This resulted in IA64 HP-UX GCC creating an instruction it
could not deal with.  I tried to create a small test case for it but
couldn't.

I did finally figure out that the reason GCC was complaining was that
REG 1715 (see the dump below) is not marked as a pointer and the
ptr_extend_plus_imm instruction will only be recognized when the base
register is marked as a pointer (basereg_operand).  The real fix would
be to figure out why the REG wasn't marked and fix that but I couldn't
figure that out so I modified ia64.md to allow any (register + immediate
offset) combination in ptr_extend_plus_imm, regardless of whether or not
the register is marked as a pointer.  I believe this is safe since the
integer constant can't be a pointer on HP-UX (it wouldn't fit in 14 bits
if it was).  To make the change I split ptr_extend_plus_imm into two
instructions, one for immediate offsets (ptr_extend_plus_imm) and one
for register offsets.  For register offsets we still want to make sure
that one and only one register has the pointer attribute set.  This is
because the addp4 instruction being used is not symetrical and thus you
need to know which register is the 32 bit address and which one is the
offset before using addp4 to extend the address to 64 bits.

This only affects 32 bit mode on HP-UX, I successfully bootstrapped and
tested the main line.  In theory this could affect 4.1 and older
versions of GCC but I have never seen it on any branch.

OK for checkin on the main line?

Steve Ellcey
sje@cup.hp.com

===============================

Bootstrap failure:

/proj/opensrc/nightly/src/trunk/gcc/tree-into-ssa.c: In function 'prepare_block_for_update':
/proj/opensrc/nightly/src/trunk/gcc/tree-into-ssa.c:1943: error: unrecognizable insn:
(insn 1197 1184 2761 33 /proj/opensrc/nightly/src/trunk/gcc/tree-flow-inline.h:941 (set (reg:DI 1717)
        (unspec:DI [
                (plus:SI (subreg/s/v:SI (reg:DI 1715) 4)
                    (const_int 4 [0x4]))
            ] 24)) -1 (insn_list:REG_DEP_TRUE 2906 (nil))
    (expr_list:REG_DEAD (reg:DI 1715)
        (expr_list:REG_EQUAL (unspec:DI [
                    (plus:SI (subreg/s/v:SI (reg:DI 1715) 4)
                        (const_int 4 [0x4]))
                ] 24)
            (nil))))


===============================

The patch:



2006-02-15  Steve Ellcey  <sje@cup.hp.com>

	* config/ia64/predicates.md (addp4_imm_operand): New predicate.
	* config/ia64/ia64.md (ptr_extend_plus_imm): Remove reg operand.
	(ptr_extend_plus_1): New.


Index: config/ia64/predicates.md
===================================================================
--- config/ia64/predicates.md	(revision 111009)
+++ config/ia64/predicates.md	(working copy)
@@ -476,6 +476,11 @@ (define_predicate "gr_reg_or_22bit_opera
        (and (match_code "const_int")
 	    (match_test "CONST_OK_FOR_J (INTVAL (op))"))))
 
+;; True if OP is a 14 bit immediate operand.
+(define_predicate "addp4_imm_operand"
+  (and (match_code "const_int")
+       (match_test "CONST_OK_FOR_I (INTVAL (op))")))
+
 ;; True if OP is a 7 bit immediate operand.
 (define_predicate "dshift_count_operand"
   (and (match_code "const_int")


Index: config/ia64/ia64.md
===================================================================
*** config/ia64/ia64.md	(revision 111009)
--- config/ia64/ia64.md	(working copy)
*************** (define_insn "ptr_extend"
*** 6299,6310 ****
  ;; Optimizations for ptr_extend
  
  (define_insn "ptr_extend_plus_imm"
    [(set (match_operand:DI 0 "gr_register_operand" "=r")
          (unspec:DI
           [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
!                    (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
           UNSPEC_ADDP4))]
    "addp4_optimize_ok (operands[1], operands[2])"
    "addp4 %0 = %2, %1"
    [(set_attr "itanium_class" "ialu")])
  
--- 6299,6320 ----
  ;; Optimizations for ptr_extend
  
  (define_insn "ptr_extend_plus_imm"
    [(set (match_operand:DI 0 "gr_register_operand" "=r")
          (unspec:DI
+          [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
+                    (match_operand:SI 2 "addp4_imm_operand" "I"))]
+          UNSPEC_ADDP4))]
+   ""
+   "addp4 %0 = %2, %1"
+   [(set_attr "itanium_class" "ialu")])
+ 
+ (define_insn "ptr_extend_plus_1"
+   [(set (match_operand:DI 0 "gr_register_operand" "=r")
+         (unspec:DI
           [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
!                    (match_operand:SI 2 "gr_register_operand" "r"))]
           UNSPEC_ADDP4))]
    "addp4_optimize_ok (operands[1], operands[2])"
    "addp4 %0 = %2, %1"
    [(set_attr "itanium_class" "ialu")])