[Committed] S/390: Comment instructions emitted by an insn pattern

Andreas Krebbel krebbel1@de.ibm.com
Wed Apr 19 10:50:00 GMT 2006


Hello,

I'm used to look for emitted machine instructions in the md file
using the editors search function. Since we heavily make use of mode
macros this has become somewhat unhandy. This patch adds comments with
the instructions emitted by an insn pattern before all define_insn which
use macros.

I've committed this to mainline after building cc1.

Bye,

-Andreas-


2006-04-19  Andreas Krebbel  <krebbel1@de.ibm.com>

	* config/s390/s390.md: Add comments with the instructions emitted
	by an insn pattern if macros are used.


Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig	2006-04-18 09:33:28.000000000 +0200
--- gcc/config/s390/s390.md	2006-04-19 10:57:41.000000000 +0200
***************
*** 467,472 ****
--- 467,473 ----
    "ltgfr\t%2,%0"
    [(set_attr "op_type" "RRE")])
  
+ ; ltr, lt, ltgr, ltg
  (define_insn "*tst<mode>_extimm"
    [(set (reg CC_REGNUM)
          (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
***************
*** 479,484 ****
--- 480,486 ----
     lt<g>\t%2,%0"
    [(set_attr "op_type" "RR<E>,RXY")])
  
+ ; ltr, lt, ltgr, ltg
  (define_insn "*tst<mode>_cconly_extimm"
    [(set (reg CC_REGNUM)
          (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
***************
*** 534,539 ****
--- 536,542 ----
    [(set_attr "op_type" "RS")
     (set_attr "atype"   "reg")])
  
+ ; ltr, ltgr
  (define_insn "*tst<mode>_cconly2"
    [(set (reg CC_REGNUM)
          (compare (match_operand:GPR 0 "register_operand" "d")
***************
*** 656,661 ****
--- 659,665 ----
     chy\t%0,%1"
    [(set_attr "op_type" "RX,RXY")])
  
+ ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg
  (define_insn "*cmp<mode>_ccs"
    [(set (reg CC_REGNUM)
          (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
***************
*** 774,779 ****
--- 778,784 ----
  
  ; (DF|SF) instructions
  
+ ; ltxbr, ltdbr, ltebr
  (define_insn "*cmp<mode>_ccs_0"
    [(set (reg CC_REGNUM)
          (compare (match_operand:FPR 0 "register_operand" "f")
***************
*** 783,788 ****
--- 788,794 ----
     [(set_attr "op_type" "RRE")
      (set_attr "type"  "fsimp<mode>")])
  
+ ; ltxr, ltdr, lter
  (define_insn "*cmp<mode>_ccs_0_ibm"
    [(set (reg CC_REGNUM)
          (compare (match_operand:FPR 0 "register_operand" "f")
***************
*** 792,797 ****
--- 798,804 ----
     [(set_attr "op_type" "<RRe>")
      (set_attr "type"  "fsimp<mode>")])
  
+ ; cxbr, cdbr, cebr, cxb, cdb, ceb
  (define_insn "*cmp<mode>_ccs"
    [(set (reg CC_REGNUM)
          (compare (match_operand:FPR 0 "register_operand" "f,f")
***************
*** 803,808 ****
--- 810,816 ----
     [(set_attr "op_type" "RRE,RXE")
      (set_attr "type"  "fsimp<mode>")])
  
+ ; cxr, cdr, cer, cx, cd, ce
  (define_insn "*cmp<mode>_ccs_ibm"
    [(set (reg CC_REGNUM)
          (compare (match_operand:FPR 0 "register_operand" "f,f")
***************
*** 2860,2865 ****
--- 2868,2874 ----
  ; extendqi(si|di)2 instruction pattern(s).
  ;
  
+ ; lbr, lgbr, lb, lgb
  (define_insn "*extendqi<mode>2_extimm"
    [(set (match_operand:GPR 0 "register_operand" "=d,d")
          (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
***************
*** 2869,2874 ****
--- 2878,2884 ----
     l<g>b\t%0,%1"
    [(set_attr "op_type" "RRE,RXY")])
  
+ ; lb, lgb
  (define_insn "*extendqi<mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
***************
*** 3020,3025 ****
--- 3030,3036 ----
      }
  })
  
+ ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
  (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
    [(set (match_operand:GPR 0 "register_operand" "=d,d")
          (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
***************
*** 3029,3034 ****
--- 3040,3046 ----
     ll<g><hc>\t%0,%1"
    [(set_attr "op_type" "RRE,RXY")])
  
+ ; llgh, llgc
  (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
***************
*** 3136,3141 ****
--- 3148,3154 ----
    DONE;
  })
  
+ ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
  (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
***************
*** 3234,3239 ****
--- 3247,3253 ----
  ; float(si|di)(tf|df|sf)2 instruction pattern(s).
  ;
  
+ ; cxgbr, cdgbr, cegbr
  (define_insn "floatdi<mode>2"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (float:FPR (match_operand:DI 1 "register_operand" "d")))]
***************
*** 3242,3247 ****
--- 3256,3262 ----
    [(set_attr "op_type" "RRE")
     (set_attr "type"    "itof" )])
  
+ ; cxfbr, cdfbr, cefbr
  (define_insn "floatsi<mode>2_ieee"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (float:FPR (match_operand:SI 1 "register_operand" "d")))]
***************
*** 3682,3687 ****
--- 3697,3703 ----
  ; add(di|si)3 instruction pattern(s).
  ;
  
+ ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag
  (define_insn "*add<mode>3"
    [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
          (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
***************
*** 3697,3702 ****
--- 3713,3719 ----
     a<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
  
+ ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
  (define_insn "*add<mode>3_carry1_cc"
    [(set (reg CC_REGNUM)
          (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
***************
*** 3713,3718 ****
--- 3730,3736 ----
     al<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RIL,RIL,RX<Y>,RXY")])
  
+ ; alr, al, aly, algr, alg
  (define_insn "*add<mode>3_carry1_cconly"
    [(set (reg CC_REGNUM)
          (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
***************
*** 3726,3731 ****
--- 3744,3750 ----
     al<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
  (define_insn "*add<mode>3_carry2_cc"
    [(set (reg CC_REGNUM)
          (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
***************
*** 3742,3747 ****
--- 3761,3767 ----
     al<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RIL,RIL,RX<Y>,RXY")])
  
+ ; alr, al, aly, algr, alg
  (define_insn "*add<mode>3_carry2_cconly"
    [(set (reg CC_REGNUM)
          (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
***************
*** 3755,3760 ****
--- 3775,3781 ----
     al<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
  (define_insn "*add<mode>3_cc"
    [(set (reg CC_REGNUM)
          (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
***************
*** 3771,3776 ****
--- 3792,3798 ----
     al<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RIL,RIL,RX<Y>,RXY")])
  
+ ; alr, al, aly, algr, alg
  (define_insn "*add<mode>3_cconly"
    [(set (reg CC_REGNUM)
          (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
***************
*** 3784,3789 ****
--- 3806,3812 ----
     al<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; alr, al, aly, algr, alg
  (define_insn "*add<mode>3_cconly2"
    [(set (reg CC_REGNUM)
          (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
***************
*** 3796,3801 ****
--- 3819,3825 ----
     al<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; ahi, afi, aghi, agfi
  (define_insn "*add<mode>3_imm_cc"
    [(set (reg CC_REGNUM)
          (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
***************
*** 3825,3830 ****
--- 3849,3855 ----
    "TARGET_HARD_FLOAT"
    "")
  
+ ; axbr, adbr, aebr, axb, adb, aeb
  (define_insn "*add<mode>3"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
          (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
***************
*** 3837,3842 ****
--- 3862,3868 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fsimp<mode>")])
  
+ ; axbr, adbr, aebr, axb, adb, aeb
  (define_insn "*add<mode>3_cc"
    [(set (reg CC_REGNUM)
  	(compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
***************
*** 3851,3856 ****
--- 3877,3883 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fsimp<mode>")])
  
+ ; axbr, adbr, aebr, axb, adb, aeb
  (define_insn "*add<mode>3_cconly"
    [(set (reg CC_REGNUM)
  	(compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
***************
*** 3864,3869 ****
--- 3891,3897 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fsimp<mode>")])
  
+ ; axr, adr, aer, ax, ad, ae
  (define_insn "*add<mode>3_ibm"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
          (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
***************
*** 4053,4058 ****
--- 4081,4087 ----
  ; sub(di|si)3 instruction pattern(s).
  ;
  
+ ; sr, s, sy, sgr, sg
  (define_insn "*sub<mode>3"
    [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
          (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
***************
*** 4065,4070 ****
--- 4094,4100 ----
     s<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; slr, sl, sly, slgr, slg
  (define_insn "*sub<mode>3_borrow_cc"
    [(set (reg CC_REGNUM)
          (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
***************
*** 4079,4084 ****
--- 4109,4115 ----
     sl<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; slr, sl, sly, slgr, slg
  (define_insn "*sub<mode>3_borrow_cconly"
    [(set (reg CC_REGNUM)
          (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
***************
*** 4092,4097 ****
--- 4123,4129 ----
     sl<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; slr, sl, sly, slgr, slg
  (define_insn "*sub<mode>3_cc"
    [(set (reg CC_REGNUM)
          (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
***************
*** 4106,4111 ****
--- 4138,4144 ----
     sl<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; slr, sl, sly, slgr, slg
  (define_insn "*sub<mode>3_cc2"
    [(set (reg CC_REGNUM)
          (compare (match_operand:GPR 1 "register_operand" "0,0,0")
***************
*** 4119,4124 ****
--- 4152,4158 ----
     sl<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; slr, sl, sly, slgr, slg
  (define_insn "*sub<mode>3_cconly"
    [(set (reg CC_REGNUM)
          (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
***************
*** 4132,4137 ****
--- 4166,4172 ----
     sl<y>\t%0,%2"
    [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
  
+ ; slr, sl, sly, slgr, slg
  (define_insn "*sub<mode>3_cconly2"
    [(set (reg CC_REGNUM)
          (compare (match_operand:GPR 1 "register_operand" "0,0,0")
***************
*** 4157,4162 ****
--- 4192,4198 ----
    "TARGET_HARD_FLOAT"
    "")
  
+ ; sxbr, sdbr, sebr, sxb, sdb, seb
  (define_insn "*sub<mode>3"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
          (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
***************
*** 4169,4174 ****
--- 4205,4211 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fsimp<mode>")])
  
+ ; sxbr, sdbr, sebr, sxb, sdb, seb
  (define_insn "*sub<mode>3_cc"
    [(set (reg CC_REGNUM)
  	(compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
***************
*** 4183,4188 ****
--- 4220,4226 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fsimp<mode>")])
  
+ ; sxbr, sdbr, sebr, sxb, sdb, seb
  (define_insn "*sub<mode>3_cconly"
    [(set (reg CC_REGNUM)
  	(compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
***************
*** 4196,4201 ****
--- 4234,4240 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fsimp<mode>")])
  
+ ; sxr, sdr, ser, sx, sd, se
  (define_insn "*sub<mode>3_ibm"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
          (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
***************
*** 4217,4222 ****
--- 4256,4262 ----
  ; add(di|si)cc instruction pattern(s).
  ;
  
+ ; alcr, alc, alcgr, alcg
  (define_insn "*add<mode>3_alc_cc"
    [(set (reg CC_REGNUM)
          (compare
***************
*** 4232,4237 ****
--- 4272,4278 ----
     alc<g>\t%0,%2"
    [(set_attr "op_type"  "RRE,RXY")])
  
+ ; alcr, alc, alcgr, alcg
  (define_insn "*add<mode>3_alc"
    [(set (match_operand:GPR 0 "register_operand" "=d,d")
          (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
***************
*** 4244,4249 ****
--- 4285,4291 ----
     alc<g>\t%0,%2"
    [(set_attr "op_type"  "RRE,RXY")])
  
+ ; slbr, slb, slbgr, slbg
  (define_insn "*sub<mode>3_slb_cc"
    [(set (reg CC_REGNUM)
          (compare
***************
*** 4259,4264 ****
--- 4301,4307 ----
     slb<g>\t%0,%2"
    [(set_attr "op_type"  "RRE,RXY")])
  
+ ; slbr, slb, slbgr, slbg
  (define_insn "*sub<mode>3_slb"
    [(set (match_operand:GPR 0 "register_operand" "=d,d")
          (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
***************
*** 4457,4462 ****
--- 4500,4506 ----
    "TARGET_HARD_FLOAT"
    "")
  
+ ; mxbr mdbr, meebr, mxb, mxb, meeb
  (define_insn "*mul<mode>3"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
          (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
***************
*** 4468,4473 ****
--- 4512,4518 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fmul<mode>")])
  
+ ; mxr, mdr, mer, mx, md, me
  (define_insn "*mul<mode>3_ibm"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
          (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
***************
*** 4479,4484 ****
--- 4524,4530 ----
    [(set_attr "op_type"  "<RRe>,<RXe>")
     (set_attr "type"     "fmul<mode>")])
  
+ ; maxbr, madbr, maebr, maxb, madb, maeb
  (define_insn "*fmadd<mode>"
    [(set (match_operand:DSF 0 "register_operand" "=f,f")
  	(plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
***************
*** 4491,4496 ****
--- 4537,4543 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fmul<mode>")])
  
+ ; msxbr, msdbr, msebr, msxb, msdb, mseb
  (define_insn "*fmsub<mode>"
    [(set (match_operand:DSF 0 "register_operand" "=f,f")
  	(minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
***************
*** 4950,4955 ****
--- 4997,5003 ----
    "TARGET_HARD_FLOAT"
    "")
  
+ ; dxbr, ddbr, debr, dxb, ddb, deb
  (define_insn "*div<mode>3"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
          (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
***************
*** 4961,4966 ****
--- 5009,5015 ----
    [(set_attr "op_type"  "RRE,RXE")
     (set_attr "type"     "fdiv<mode>")])
  
+ ; dxr, ddr, der, dx, dd, de
  (define_insn "*div<mode>3_ibm"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
          (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
***************
*** 5878,5883 ****
--- 5927,5933 ----
    "lcgfr\t%0,%1"
    [(set_attr "op_type"  "RRE")])
  
+ ; lcr, lcgr
  (define_insn "*neg<mode>2_cc"
    [(set (reg CC_REGNUM)
          (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
***************
*** 5887,5893 ****
    "s390_match_ccmode (insn, CCAmode)"
    "lc<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
!   
  (define_insn "*neg<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
--- 5937,5944 ----
    "s390_match_ccmode (insn, CCAmode)"
    "lc<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
! 
! ; lcr, lcgr
  (define_insn "*neg<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
***************
*** 5896,5902 ****
    "s390_match_ccmode (insn, CCAmode)"
    "lc<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
!   
  (define_insn "*neg<mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
--- 5947,5954 ----
    "s390_match_ccmode (insn, CCAmode)"
    "lc<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
! 
! ; lcr, lcgr
  (define_insn "*neg<mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
***************
*** 5945,5950 ****
--- 5997,6003 ----
    "TARGET_HARD_FLOAT"
    "")
  
+ ; lcxbr, lcdbr, lcebr
  (define_insn "*neg<mode>2_cc"
    [(set (reg CC_REGNUM)
          (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
***************
*** 5955,5961 ****
    "lc<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
!   
  (define_insn "*neg<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
--- 6008,6015 ----
    "lc<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
! 
! ; lcxbr, lcdbr, lcebr
  (define_insn "*neg<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
***************
*** 5965,5971 ****
    "lc<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
!   
  (define_insn "*neg<mode>2"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
--- 6019,6026 ----
    "lc<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
! 
! ; lcxbr, lcdbr, lcebr
  (define_insn "*neg<mode>2"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
***************
*** 5975,5980 ****
--- 6030,6036 ----
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
  
+ ; lcxr, lcdr, lcer
  (define_insn "*neg<mode>2_ibm"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
***************
*** 6013,6018 ****
--- 6069,6075 ----
    "lpgfr\t%0,%1"
    [(set_attr "op_type"  "RRE")])
  
+ ; lpr, lpgr
  (define_insn "*abs<mode>2_cc"
    [(set (reg CC_REGNUM)
          (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
***************
*** 6022,6028 ****
    "s390_match_ccmode (insn, CCAmode)"
    "lp<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
!   
  (define_insn "*abs<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
--- 6079,6086 ----
    "s390_match_ccmode (insn, CCAmode)"
    "lp<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
! 
! ; lpr, lpgr  
  (define_insn "*abs<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
***************
*** 6031,6037 ****
    "s390_match_ccmode (insn, CCAmode)"
    "lp<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
!   
  (define_insn "abs<mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
--- 6089,6096 ----
    "s390_match_ccmode (insn, CCAmode)"
    "lp<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
! 
! ; lpr, lpgr
  (define_insn "abs<mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
***************
*** 6052,6057 ****
--- 6111,6117 ----
    "TARGET_HARD_FLOAT"
    "")
  
+ ; lpxbr, lpdbr, lpebr
  (define_insn "*abs<mode>2_cc"
    [(set (reg CC_REGNUM)
          (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
***************
*** 6062,6068 ****
    "lp<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
!   
  (define_insn "*abs<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
--- 6122,6129 ----
    "lp<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
! 
! ; lpxbr, lpdbr, lpebr
  (define_insn "*abs<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
***************
*** 6072,6078 ****
    "lp<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
!   
  (define_insn "*abs<mode>2"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
--- 6133,6140 ----
    "lp<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
! 
! ; lpxbr, lpdbr, lpebr
  (define_insn "*abs<mode>2"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
***************
*** 6082,6087 ****
--- 6144,6150 ----
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
  
+ ; lpxr, lpdr, lper
  (define_insn "*abs<mode>2_ibm"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
***************
*** 6120,6125 ****
--- 6183,6189 ----
    "lngfr\t%0,%1"
    [(set_attr "op_type" "RRE")])
  
+ ; lnr, lngr
  (define_insn "*negabs<mode>2_cc"
    [(set (reg CC_REGNUM)
          (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
***************
*** 6129,6135 ****
    "s390_match_ccmode (insn, CCAmode)"
    "ln<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
!   
  (define_insn "*negabs<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
--- 6193,6200 ----
    "s390_match_ccmode (insn, CCAmode)"
    "ln<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
! 
! ; lnr, lngr
  (define_insn "*negabs<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
***************
*** 6138,6144 ****
    "s390_match_ccmode (insn, CCAmode)"
    "ln<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
!   
  (define_insn "*negabs<mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d")
  	(neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
--- 6203,6210 ----
    "s390_match_ccmode (insn, CCAmode)"
    "ln<g>r\t%0,%1"
    [(set_attr "op_type"  "RR<E>")])
! 
! ; lnr, lngr
  (define_insn "*negabs<mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d")
  	(neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
***************
*** 6151,6156 ****
--- 6217,6223 ----
  ; Floating point
  ;
  
+ ; lnxbr, lndbr, lnebr
  (define_insn "*negabs<mode>2_cc"
    [(set (reg CC_REGNUM)
          (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
***************
*** 6161,6167 ****
    "ln<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
!   
  (define_insn "*negabs<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
--- 6228,6235 ----
    "ln<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
! 
! ; lnxbr, lndbr, lnebr
  (define_insn "*negabs<mode>2_cconly"
    [(set (reg CC_REGNUM)
          (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
***************
*** 6171,6177 ****
    "ln<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
!   
  (define_insn "*negabs<mode>2"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
--- 6239,6246 ----
    "ln<xde>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
     (set_attr "type"     "fsimp<mode>")])
! 
! ; lnxbr, lndbr, lnebr
  (define_insn "*negabs<mode>2"
    [(set (match_operand:FPR 0 "register_operand" "=f")
          (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
***************
*** 6189,6194 ****
--- 6258,6264 ----
  ; sqrt(df|sf)2 instruction pattern(s).
  ;
  
+ ; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
  (define_insn "sqrt<mode>2"
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
  	(sqrt:FPR (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
***************
*** 6269,6274 ****
--- 6339,6345 ----
  ; rotl(di|si)3 instruction pattern(s).
  ;
  
+ ; rll, rllg
  (define_insn "rotl<mode>3"
    [(set (match_operand:GPR 0 "register_operand" "=d")
  	(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
***************
*** 6278,6283 ****
--- 6349,6355 ----
    [(set_attr "op_type"  "RSE")
     (set_attr "atype"    "reg")])
  
+ ; rll, rllg
  (define_insn "*rotl<mode>3_and"
    [(set (match_operand:GPR 0 "register_operand" "=d")
  	(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
***************
*** 6304,6309 ****
--- 6376,6382 ----
    ""
    "")
  
+ ; sldl, srdl
  (define_insn "*<shift>di3_31"
    [(set (match_operand:DI 0 "register_operand" "=d")
          (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
***************
*** 6313,6318 ****
--- 6386,6392 ----
    [(set_attr "op_type"  "RS")
     (set_attr "atype"    "reg")])
  
+ ; sll, srl, sllg, srlg
  (define_insn "*<shift><mode>3"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
***************
*** 6322,6327 ****
--- 6396,6402 ----
    [(set_attr "op_type"  "RS<E>")
     (set_attr "atype"    "reg")])
  
+ ; sldl, srdl
  (define_insn "*<shift>di3_31_and"
    [(set (match_operand:DI 0 "register_operand" "=d")
          (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
***************
*** 6332,6337 ****
--- 6407,6413 ----
    [(set_attr "op_type"  "RS")
     (set_attr "atype"    "reg")])
  
+ ; sll, srl, sllg, srlg
  (define_insn "*<shift><mode>3_and"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
***************
*** 6388,6393 ****
--- 6464,6470 ----
    [(set_attr "op_type"  "RS")
     (set_attr "atype"    "reg")])
  
+ ; sra, srag
  (define_insn "*ashr<mode>3_cc"
    [(set (reg CC_REGNUM)
          (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
***************
*** 6400,6405 ****
--- 6477,6483 ----
    [(set_attr "op_type"  "RS<E>")
     (set_attr "atype"    "reg")])
  
+ ; sra, srag
  (define_insn "*ashr<mode>3_cconly"
    [(set (reg CC_REGNUM)
          (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
***************
*** 6411,6416 ****
--- 6489,6495 ----
    [(set_attr "op_type"  "RS<E>")
     (set_attr "atype"    "reg")])
  
+ ; sra, srag
  (define_insn "*ashr<mode>3"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
***************
*** 6462,6467 ****
--- 6541,6547 ----
    [(set_attr "op_type"  "RS")
     (set_attr "atype"    "reg")])
  
+ ; sra, srag
  (define_insn "*ashr<mode>3_cc_and"
    [(set (reg CC_REGNUM)
          (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
***************
*** 6475,6480 ****
--- 6555,6561 ----
    [(set_attr "op_type"  "RS<E>")
     (set_attr "atype"    "reg")])
  
+ ; sra, srag
  (define_insn "*ashr<mode>3_cconly_and"
    [(set (reg CC_REGNUM)
          (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
***************
*** 6487,6492 ****
--- 6568,6574 ----
    [(set_attr "op_type"  "RS<E>")
     (set_attr "atype"    "reg")])
  
+ ; sra, srag
  (define_insn "*ashr<mode>3_and"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
***************
*** 7376,7381 ****
--- 7458,7464 ----
    s390_compare_emitted = operands[4];
  })
  
+ ; cds, cdsg
  (define_insn "*sync_compare_and_swap<mode>"
    [(set (match_operand:DP 0 "register_operand" "=r")
  	(match_operand:DP 1 "memory_operand" "+Q"))
***************
*** 7392,7397 ****
--- 7475,7481 ----
    [(set_attr "op_type" "RS<TE>")
     (set_attr "type"   "sem")])
  
+ ; cs, csg
  (define_insn "*sync_compare_and_swap<mode>"
    [(set (match_operand:GPR 0 "register_operand" "=r")
  	(match_operand:GPR 1 "memory_operand" "+Q"))



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