SH patch applied

[Kaz Kojima]

Joern RENNECKE <joern.rennecke@st.com> wrote:
> reload complained because HARD_REGNO_MODE_OK disallowed
> V4SFmode in GENERAL_REGS.  Allowing that also causes register
> allocation to use GENERAL_REGS in the first place.  An and with a
> J16 constraint can also be done with FP_REGS using mov.ls from r63.
> A natural way to implement this would use an fr (or rf) constraint in
> one of the alternatives.  While looking at this I also found that we were
> missing a register class for an fr constraint.  I've tested the attached
> patch over the weekend for sh-elf and sh64-elf, and checked it in now.

On sh64-unknown-linux-gnu, now -O0 cases pass, though simd-4.c
still fails with -O1 and higher:

ORIG/gcc/gcc/testsuite/gcc.c-torture/compile/simd-4.c:15: error: insn does not satisfy its constraints:
(insn 95 13 15 0 (set (reg/v:V4SF 9 r9 [orig:160 temp ] [160])
        (reg:V4SF 68 fr4)) 197 {*movv4sf_i} (nil)
    (nil))
ORIG/gcc/gcc/testsuite/gcc.c-torture/compile/simd-4.c:15: internal compiler error: in reload_cse_simplify_operands, at postreload.c:393

It seems that the attached patch gets rid of this ICE.  How does it
look like?

Regards,
	kaz
--
	* config/sh/sh.md (*movv4sf_i): Add general register cases to
	the constraints.

--- ORIG/gcc/gcc/config/sh/sh.md	Wed Sep  7 06:16:56 2005
+++ LOCAL/gcc/gcc/config/sh/sh.md	Tue Sep 13 09:07:36 2005
@@ -6213,8 +6213,8 @@ label:
 }")
 
 (define_insn_and_split "*movv4sf_i"
-  [(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m")
-	(match_operand:V4SF 1 "general_operand" "fZ,m,fZ"))]
+  [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
+	(match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
   "TARGET_SHMEDIA_FPU"
   "#"
   "&& reload_completed"