Committed: Fix some ARM 64-bit H_W_I bugs

[Daniel Jacobowitz]

I recently moved my build/test scripts to a 64-bit host.  Cross gcc fell
down trying to compile a bitfield operation in gcc/real.c, with improperly
sign extended CONST_INTs.

Paul fixed one place where this could happen a while ago; this gets all of
the others in the insv pattern.  Committed as obvious to HEAD and
csl-arm-branch.

-- 
Daniel Jacobowitz
CodeSourcery, LLC

2005-10-05  Daniel Jacobowitz  <dan@codesourcery.com>

	* config/arm/arm.md (insv): Use gen_int_mode in more places.

Index: gcc/gcc/config/arm/arm.md
===================================================================
--- gcc.orig/gcc/config/arm/arm.md	2005-10-05 10:57:23.000000000 -0400
+++ gcc/gcc/config/arm/arm.md	2005-10-05 11:20:30.000000000 -0400
@@ -1902,7 +1902,8 @@
 	HOST_WIDE_INT op3_value = mask & INTVAL (operands[3]);
 	HOST_WIDE_INT mask2 = ((mask & ~op3_value) << start_bit);
 
-	emit_insn (gen_andsi3 (op1, operands[0], GEN_INT (~mask2)));
+	emit_insn (gen_andsi3 (op1, operands[0],
+			       gen_int_mode (~mask2, SImode)));
 	emit_insn (gen_iorsi3 (subtarget, op1,
 			       gen_int_mode (op3_value << start_bit, SImode)));
       }
@@ -1940,7 +1941,7 @@
       }
     else
       {
-	rtx op0 = GEN_INT (mask);
+	rtx op0 = gen_int_mode (mask, SImode);
 	rtx op1 = gen_reg_rtx (SImode);
 	rtx op2 = gen_reg_rtx (SImode);
 
@@ -1959,7 +1960,7 @@
 	    && (const_ok_for_arm (mask << start_bit)
 		|| const_ok_for_arm (~(mask << start_bit))))
 	  {
-	    op0 = GEN_INT (~(mask << start_bit));
+	    op0 = gen_int_mode (~(mask << start_bit), SImode);
 	    emit_insn (gen_andsi3 (op2, operands[0], op0));
 	  }
 	else