Patch to support ppc 405 and 440 half-word multiply instructions
Joseph S. Myers
joseph@codesourcery.com
Mon Nov 21 18:38:00 GMT 2005
This patch, from csl-ppc4xx-branch, implements support for the
half-word multiply and multiply-accumulate instructions on the IBM
PowerPC 405 and 440.
Tested with --with-cpu=440 with a cross-compiler to
powerpc-ibm-linux-gnu. OK to commit to mainline?
2005-11-20 Joseph S. Myers <joseph@codesourcery.com>
* config/rs6000/rs6000.opt (mmulhw): New option.
* doc/invoke.texi (-mmulhw): Document.
* config/rs6000/rs6000.c (rs6000_override_options): Enable -mmulhw
for 405 and 440.
* config/rs6000/rs6000.md: Add half-word multiply and
multiply-accumulate instructions for 405 and 440.
testsuite:
2005-11-20 Joseph S. Myers <joseph@codesourcery.com>
* gcc.target/powerpc/405-macchw-1.c,
gcc.target/powerpc/405-macchw-2.c,
gcc.target/powerpc/405-macchwu-1.c,
gcc.target/powerpc/405-macchwu-2.c,
gcc.target/powerpc/405-machhw-1.c,
gcc.target/powerpc/405-machhw-2.c,
gcc.target/powerpc/405-machhwu-1.c,
gcc.target/powerpc/405-machhwu-2.c,
gcc.target/powerpc/405-maclhw-1.c,
gcc.target/powerpc/405-maclhw-2.c,
gcc.target/powerpc/405-maclhwu-1.c,
gcc.target/powerpc/405-maclhwu-2.c,
gcc.target/powerpc/405-mulchw-1.c,
gcc.target/powerpc/405-mulchw-2.c,
gcc.target/powerpc/405-mulchwu-1.c,
gcc.target/powerpc/405-mulchwu-2.c,
gcc.target/powerpc/405-mulhhw-1.c,
gcc.target/powerpc/405-mulhhw-2.c,
gcc.target/powerpc/405-mulhhwu-1.c,
gcc.target/powerpc/405-mulhhwu-2.c,
gcc.target/powerpc/405-mullhw-1.c,
gcc.target/powerpc/405-mullhw-2.c,
gcc.target/powerpc/405-mullhwu-1.c,
gcc.target/powerpc/405-mullhwu-2.c,
gcc.target/powerpc/405-nmacchw-1.c,
gcc.target/powerpc/405-nmacchw-2.c,
gcc.target/powerpc/405-nmachhw-1.c,
gcc.target/powerpc/405-nmachhw-2.c,
gcc.target/powerpc/405-nmaclhw-1.c,
gcc.target/powerpc/405-nmaclhw-2.c,
gcc.target/powerpc/440-macchw-1.c,
gcc.target/powerpc/440-macchw-2.c,
gcc.target/powerpc/440-macchwu-1.c,
gcc.target/powerpc/440-macchwu-2.c,
gcc.target/powerpc/440-machhw-1.c,
gcc.target/powerpc/440-machhw-2.c,
gcc.target/powerpc/440-machhwu-1.c,
gcc.target/powerpc/440-machhwu-2.c,
gcc.target/powerpc/440-maclhw-1.c,
gcc.target/powerpc/440-maclhw-2.c,
gcc.target/powerpc/440-maclhwu-1.c,
gcc.target/powerpc/440-maclhwu-2.c,
gcc.target/powerpc/440-mulchw-1.c,
gcc.target/powerpc/440-mulchw-2.c,
gcc.target/powerpc/440-mulchwu-1.c,
gcc.target/powerpc/440-mulchwu-2.c,
gcc.target/powerpc/440-mulhhw-1.c,
gcc.target/powerpc/440-mulhhw-2.c,
gcc.target/powerpc/440-mulhhwu-1.c,
gcc.target/powerpc/440-mulhhwu-2.c,
gcc.target/powerpc/440-mullhw-1.c,
gcc.target/powerpc/440-mullhw-2.c,
gcc.target/powerpc/440-mullhwu-1.c,
gcc.target/powerpc/440-mullhwu-2.c,
gcc.target/powerpc/440-nmacchw-1.c,
gcc.target/powerpc/440-nmacchw-2.c,
gcc.target/powerpc/440-nmachhw-1.c,
gcc.target/powerpc/440-nmachhw-2.c,
gcc.target/powerpc/440-nmaclhw-1.c,
gcc.target/powerpc/440-nmaclhw-2.c: New tests.
diff -rupN GCC.orig/gcc/config/rs6000/rs6000.c GCC/gcc/config/rs6000/rs6000.c
--- GCC.orig/gcc/config/rs6000/rs6000.c 2005-11-15 09:16:52.000000000 +0000
+++ GCC/gcc/config/rs6000/rs6000.c 2005-11-20 17:19:12.000000000 +0000
@@ -1107,10 +1107,12 @@ rs6000_override_options (const char *def
= {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"403", PROCESSOR_PPC403,
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
- {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
- {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
- {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
- {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
+ {"405", PROCESSOR_PPC405,
+ POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
+ {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_MULHW},
+ {"440", PROCESSOR_PPC440,
+ POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
+ {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_MULHW},
{"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
{"601", PROCESSOR_PPC601,
MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
@@ -1180,7 +1182,7 @@ rs6000_override_options (const char *def
POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
- | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
+ | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW)
};
rs6000_init_hard_regno_mode_ok ();
diff -rupN GCC.orig/gcc/config/rs6000/rs6000.md GCC/gcc/config/rs6000/rs6000.md
--- GCC.orig/gcc/config/rs6000/rs6000.md 2005-11-16 22:57:10.000000000 +0000
+++ GCC/gcc/config/rs6000/rs6000.md 2005-11-20 17:17:24.000000000 +0000
@@ -878,6 +878,470 @@
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
+;; IBM 405 and 440 half-word multiplication operations.
+
+(define_insn "*macchwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16))
+ (sign_extend:SI
+ (match_dup 1)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "macchw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*macchw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "macchw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*macchwuc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (lshiftrt:SI
+ (match_dup 2)
+ (const_int 16))
+ (zero_extend:SI
+ (match_dup 1)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "macchwu. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*macchwu"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "macchwu %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*machhwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_dup 1)
+ (const_int 16))
+ (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "machhw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*machhw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "machhw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*machhwuc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (lshiftrt:SI
+ (match_dup 1)
+ (const_int 16))
+ (lshiftrt:SI
+ (match_dup 2)
+ (const_int 16)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "machhwu. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*machhwu"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (lshiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "machhwu %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (sign_extend:SI
+ (match_dup 1))
+ (sign_extend:SI
+ (match_dup 2)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "maclhw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*maclhw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "maclhw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwuc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (zero_extend:SI
+ (match_dup 1))
+ (zero_extend:SI
+ (match_dup 2)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "maclhwu. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwu"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "maclhwu %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*nmacchwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+ (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r"))))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (minus:SI (match_dup 4)
+ (mult:SI (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16))
+ (sign_extend:SI
+ (match_dup 1)))))]
+ "TARGET_MULHW"
+ "nmacchw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*nmacchw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+ (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))))]
+ "TARGET_MULHW"
+ "nmacchw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*nmachhwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+ (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (minus:SI (match_dup 4)
+ (mult:SI (ashiftrt:SI
+ (match_dup 1)
+ (const_int 16))
+ (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16)))))]
+ "TARGET_MULHW"
+ "nmachhw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*nmachhw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+ (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))))]
+ "TARGET_MULHW"
+ "nmachhw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*nmaclhwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+ (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r"))))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (minus:SI (match_dup 4)
+ (mult:SI (sign_extend:SI
+ (match_dup 1))
+ (sign_extend:SI
+ (match_dup 2)))))]
+ "TARGET_MULHW"
+ "nmaclhw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*nmaclhw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+ (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))))]
+ "TARGET_MULHW"
+ "nmaclhw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16))
+ (sign_extend:SI
+ (match_dup 1))))]
+ "TARGET_MULHW"
+ "mulchw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mulchw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r"))))]
+ "TARGET_MULHW"
+ "mulchw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwuc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (mult:SI (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (lshiftrt:SI
+ (match_dup 2)
+ (const_int 16))
+ (zero_extend:SI
+ (match_dup 1))))]
+ "TARGET_MULHW"
+ "mulchwu. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwu"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r"))))]
+ "TARGET_MULHW"
+ "mulchwu %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (ashiftrt:SI
+ (match_dup 1)
+ (const_int 16))
+ (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16))))]
+ "TARGET_MULHW"
+ "mulhhw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))))]
+ "TARGET_MULHW"
+ "mulhhw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwuc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (mult:SI (lshiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (lshiftrt:SI
+ (match_dup 1)
+ (const_int 16))
+ (lshiftrt:SI
+ (match_dup 2)
+ (const_int 16))))]
+ "TARGET_MULHW"
+ "mulhhwu. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwu"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (lshiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))))]
+ "TARGET_MULHW"
+ "mulhhwu %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mullhwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (sign_extend:SI
+ (match_dup 1))
+ (sign_extend:SI
+ (match_dup 2))))]
+ "TARGET_MULHW"
+ "mullhw. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mullhw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r"))))]
+ "TARGET_MULHW"
+ "mullhw %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mullhwuc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (mult:SI (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (zero_extend:SI
+ (match_dup 1))
+ (zero_extend:SI
+ (match_dup 2))))]
+ "TARGET_MULHW"
+ "mullhwu. %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
+(define_insn "*mullhwu"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (mult:SI (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r"))))]
+ "TARGET_MULHW"
+ "mullhwu %0, %1, %2"
+ [(set_attr "type" "imul3")])
+
(define_split
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
diff -rupN GCC.orig/gcc/config/rs6000/rs6000.opt GCC/gcc/config/rs6000/rs6000.opt
--- GCC.orig/gcc/config/rs6000/rs6000.opt 2005-11-15 09:16:52.000000000 +0000
+++ GCC/gcc/config/rs6000/rs6000.opt 2005-11-20 17:17:24.000000000 +0000
@@ -68,6 +68,10 @@ maltivec
Target Report Mask(ALTIVEC)
Use AltiVec instructions
+mmulhw
+Target Report Mask(MULHW)
+Use 4xx half-word multiply instructions
+
mmultiple
Target Report Mask(MULTIPLE)
Generate load/store multiple instructions
diff -rupN GCC.orig/gcc/doc/invoke.texi GCC/gcc/doc/invoke.texi
--- GCC.orig/gcc/doc/invoke.texi 2005-11-16 15:08:37.000000000 +0000
+++ GCC/gcc/doc/invoke.texi 2005-11-20 17:18:33.000000000 +0000
@@ -659,6 +659,7 @@ See RS/6000 and PowerPC Options.
-mspe -mno-spe @gol
-mspe=yes -mspe=no @gol
-mvrsave -mno-vrsave @gol
+-mmulhw -mno-mulhw @gol
-mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol
-mprototype -mno-prototype @gol
-msim -mmvme -mads -myellowknife -memb -msdata @gol
@@ -10974,7 +10975,8 @@ following options: @option{-maltivec}, @
@option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple},
@option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower},
@option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
-@option{-mpowerpc-gfxopt}, @option{-mstring}. The particular options
+@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}.
+The particular options
set for any particular CPU will vary between compiler versions,
depending on what setting seems to produce optimal code for that CPU;
it doesn't necessarily reflect the actual hardware's capabilities. If
@@ -11236,6 +11238,15 @@ Generate code that uses (does not use) t
accumulate instructions. These instructions are generated by default if
hardware floating is used.
+@item -mmulhw
+@itemx -mno-mulhw
+@opindex mmulhw
+@opindex mno-mulhw
+Generate code that uses (does not use) the half-word multiply and
+multiply-accumulate instructions on the IBM 405 and 440 processors.
+These instructions are generated by default when targetting those
+processors.
+
@item -mno-bit-align
@itemx -mbit-align
@opindex mno-bit-align
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of macchw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "macchw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of macchw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "macchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of macchwu on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "macchwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (unsigned short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of macchwu. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "macchwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (unsigned short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of machhw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "machhw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of machhw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "machhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of machhwu on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "machhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of machhwu. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "machhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of maclhw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "maclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (short)b * (short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of maclhw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "maclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (short)b * (short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of maclhwu on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "maclhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (unsigned short)b * (unsigned short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of maclhwu. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "maclhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (unsigned short)b * (unsigned short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mulchw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mulchw " } } */
+
+int
+f(int b, int c)
+{
+ int a = (short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mulchw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mulchw\\. " } } */
+
+int
+f(int b, int c)
+{
+ int a = (short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mulchwu on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mulchwu " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (unsigned short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mulchwu. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mulchwu\\. " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (unsigned short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mulhhw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mulhhw " } } */
+
+int
+f(int b, int c)
+{
+ int a = (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mulhhw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mulhhw\\. " } } */
+
+int
+f(int b, int c)
+{
+ int a = (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mulhhwu on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mulhhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mulhhwu. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mulhhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mullhw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mullhw " } } */
+
+int
+f(int b, int c)
+{
+ int a = (short)b * (short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mullhw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mullhw\\. " } } */
+
+int
+f(int b, int c)
+{
+ int a = (short)b * (short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mullhwu on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mullhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (unsigned short)b * (unsigned short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mullhwu. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "mullhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (unsigned short)b * (unsigned short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of nmacchw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "nmacchw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of nmacchw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "nmacchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of nmachhw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "nmachhw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of nmachhw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "nmachhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of nmaclhw on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "nmaclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (short)b * (short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of nmaclhw. on 405. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+
+/* { dg-final { scan-assembler "nmaclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (short)b * (short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of macchw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of macchw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of macchwu on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (unsigned short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of macchwu. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (unsigned short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of machhw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of machhw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of machhwu on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of machhwu. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of maclhw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (short)b * (short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of maclhw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a += (short)b * (short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of maclhwu on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (unsigned short)b * (unsigned short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of maclhwu. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+ a += (unsigned short)b * (unsigned short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mulchw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchw " } } */
+
+int
+f(int b, int c)
+{
+ int a = (short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mulchw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchw\\. " } } */
+
+int
+f(int b, int c)
+{
+ int a = (short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mulchwu on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchwu " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (unsigned short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mulchwu. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchwu\\. " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (unsigned short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mulhhw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhw " } } */
+
+int
+f(int b, int c)
+{
+ int a = (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mulhhw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhw\\. " } } */
+
+int
+f(int b, int c)
+{
+ int a = (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mulhhwu on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mulhhwu. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mullhw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhw " } } */
+
+int
+f(int b, int c)
+{
+ int a = (short)b * (short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mullhw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhw\\. " } } */
+
+int
+f(int b, int c)
+{
+ int a = (short)b * (short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of mullhwu on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (unsigned short)b * (unsigned short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of mullhwu. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+ unsigned int a = (unsigned short)b * (unsigned short)c;
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of nmacchw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmacchw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (short)b * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of nmacchw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmacchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (short)b * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of nmachhw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmachhw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (b >> 16) * (c >> 16);
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of nmachhw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmachhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (b >> 16) * (c >> 16);
+ if (!a)
+ return 10;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c GCC/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,14 @@
+/* Test generation of nmaclhw on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmaclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (short)b * (short)c;
+ return a;
+}
diff -rupN GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c GCC/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c
--- GCC.orig/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c 1970-01-01 00:00:00.000000000 +0000
+++ GCC/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c 2005-11-20 17:17:24.000000000 +0000
@@ -0,0 +1,16 @@
+/* Test generation of nmaclhw. on 440. */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmaclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+ a -= (short)b * (short)c;
+ if (!a)
+ return 10;
+ return a;
+}
--
Joseph S. Myers http://www.srcf.ucam.org/~jsm28/gcc/
jsm@polyomino.org.uk (personal mail)
joseph@codesourcery.com (CodeSourcery mail)
jsm28@gcc.gnu.org (Bugzilla assignments and CCs)
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