[PATCH] Fix Bug target/21684 SHIFT_COUNT_TRUNCATED incorrectly defined for MCORE

[Kevin Winchester]

The problem is that the MCORE shift instructions truncate shift operands to 6 
bits, rather than the 5 bits that would be expected.

In mcore.h, SHIFT_COUNT_TRUNCATED is defined as 1, when it shouldn't be 
defined at all.

It is possible that TARGET_SHIFT_TRUNCATION_MASK should be added, but I wasn't 
sure where or how to do that, so I'll leave it at this simple patch.


Changelog:
	* gcc/config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Removed
	definition as it is not valid for the MCORE.

Patch:

Index: gcc/config/mcore/mcore.h
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/mcore/mcore.h,v
retrieving revision 1.76
diff -c -3 -p -r1.76 mcore.h
*** gcc/config/mcore/mcore.h    6 May 2005 13:58:16 -0000       1.76
--- gcc/config/mcore/mcore.h    21 May 2005 13:33:45 -0000
*************** extern const enum reg_class reg_class_fr
*** 820,832 ****
   /* Nonzero if access to memory by bytes is slow and undesirable.  */
   #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES

- /* Immediate shift counts are truncated by the output routines (or was it
-    the assembler?).  Shift counts in a register are truncated by ARM.  Note
-    that the native compiler puts too large (> 32) immediate shift counts
-    into a register and shifts by the register, letting the ARM decide what
-    to do instead of doing that itself.  */
- #define SHIFT_COUNT_TRUNCATED 1
-
   /* All integers have the same format so truncation is easy.  */
   #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC)  1

--- 820,825 ----