[patch] Add DFA-based pipeline descriptions for MIPS 24K core.
David Ung
davidu@mips.com
Fri May 6 16:06:00 GMT 2005
> > ;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
> > (define_insn_reservation "r24k_int_load" 2
> > (and (eq_attr "cpu" "24k,24kx")
> > (and (eq_attr "type" "load,prefetch")
> > (eq_attr "mode" "!SF,DF")))
> > "r24k_iss+r24k_ixu_arith")
>
> This isn't good. Remember, you can't use the mode to tell the difference
> between operations involving integer _registers_ and those involving
> floating-point registers.
>
> As part of his SB-1 work, Jim split the "load" attribute into
> "load" (for loads of integer registers), "fpload" (for loads of
> floating-point registers) and "fpidxload" (for indexed FPR loads).
> So I think you should just be using this reservation for all "load"
> instructions.
done.
>
> > ;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
> > ;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
> > ;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
> > ;; xor, xori
> > (define_insn_reservation "r24k_int_arith" 1
> > (and (eq_attr "cpu" "24k,24kx")
> > (eq_attr "type" "arith,const,nop,shift,slt"))
> > "r24k_iss+r24k_ixu_arith")
>
> MOVN and MOVZ have type "condmove". (So do floating-point condmoves though.)
> You should either split the attribute into two or add a comment saying that
> movz and movn are not yet matched.
I've added comments for the integer movs. Will do the spliting later.
> > ;; 5. Cop: cfc1, di, ei, mfc0, mtc0
> > (define_insn_reservation "r24k_int_cop" 3
> > (and (eq_attr "cpu" "24k,24kx")
> > (and (eq_attr "type" "xfer")
> > (eq_attr "mode" "!SF,DF")))
> > "r24k_iss+r24k_ixu_arith")
>
> This is why I said in my previous mail:
>
> If I've read your pipeline description correctly, you just want a way
> of distinguishing coprocessor 1 transfers from coprocessor 0 transfers.
> I'm not sure how much that will matter in practice (does anyone actually
> use gcc's coprocessor 0 extensions?) but if you do want to keep them
> separate, please just split "xfer" into two attribute values. I realise
> that involves changing more code, but I think it's the right thing to do.
> Extra points for submitting the split as a separate patch.
>
> As before, "mode" is not the right test. "xfer" is used for move
> patterns, which have a single value for "mode", and which generally have
> xfer alternatives for all coprocessors. E.g. "movsf" and "movsi" both have
> xfer alternatives for all coprocessors, but your reservation will identify
> all "movsi" instructions as using coprocessor 0 and all "movsf" instructions
> as using the FPU.
>
> If you don't want to split xfer, I suggest you just comment out this
> alternative and assume all xfers are FPU xfers.
I've commented out this reservation since gcc4 don't really generate
these special cop instructions yet. It was there for completeness
really.
> > ;; 6. Store
> > (define_insn_reservation "r24k_int_store" 1
> > (and (eq_attr "cpu" "24k,24kx")
> > (and (eq_attr "type" "store")
> > (eq_attr "mode" "!SF,DF,unknown")))
> > "r24k_iss+r24k_ixu_arith")
>
> Similar comment to loads. "store" is now for integer registers only;
> "fpstore" is for floating-point registers.
>
> > ;; Unknown stores assumed to transfer integers.
> > (define_insn_reservation "r24k_unknown_store" 1
> > (and (eq_attr "cpu" "24k,24kx")
> > (and (eq_attr "type" "store")
> > (eq_attr "mode" "unknown")))
> > "r24k_iss+r24k_ixu_arith")
>
> Why did you exclude "unknown" in the previous reservation and then
> implement the same behaviour using a second reservation?
in mips.md there's this pattern for .cprestore and it returns with
"store" type:
(define_insn "cprestore"
[(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
UNSPEC_CPRESTORE)]
""
{
if (set_nomacro && which_alternative == 1)
return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
else
return ".cprestore\t%0";
}
[(set_attr "type" "store")
(set_attr "length" "4,12")])
and we don't want this pattern to match as r24k_int_store.
>
> > ;; fload
> > (define_insn_reservation "r24k_fload" 6
> > (and (eq_attr "cpu" "24k")
> > (and (eq_attr "type" "fpload,prefetch,prefetchx")
> > (eq_attr "mode" "SF,DF")))
> > "r24k_fpu_iss")
>
> Again, this should match all "fpload"s. Since you include prefetchx,
> I assume it should also match "fpidxload". Same comment for the r24kx
> version.
done.
I've now separated the prefetch instructions into its own reservations,
and it'll have its affect as bypasses to instructions that uses the same
base register as the prefetch. This added more bypasses, but avoids
overloading "r24k_int_load".
new patch attached below..
David.
2005-05-06 David Ung <davidu@mips.com>
* config/mips/mips.h (processor_type): Add names for the 24K.
* config/mips/mips.c (mips_cpu_info_table): Add names for the 24K
processor family.
* config/mips/mips.md (cnv_mode): New attribute for recording the
conversion types of float convert insns.
(cpu): Add 24k and 24kx.
(include): Include 24k.md file.
("truncdfsf2", "extendsfdf2", "fix_truncdfsi2_insn")
("fix_truncdfsi2_macro", "fix_truncdfdi2", "fix_truncsfdi2")
("floatsidf2", "floatdidf2", "floatsisf2")
("floatdisf2"): Setup cnv_mode.
("fix_truncsfsi2_insn", "fix_truncsfsi2_macro"): Changed mode to
SF and setup cnv_mode.
* config/mips/24k.md: New file, contains 24k DFA pipeline
description.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/mips.c,v
retrieving revision 1.498
diff -c -3 -r1.498 mips.c
*** config/mips/mips.c 26 Apr 2005 17:55:23 -0000 1.498
--- config/mips/mips.c 6 May 2005 15:37:31 -0000
***************
*** 700,705 ****
--- 700,709 ----
/* MIPS32 Release 2 */
{ "m4k", PROCESSOR_M4K, 33 },
+ { "24k", PROCESSOR_24K, 33 },
+ { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
+ { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
+ { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
/* MIPS64 */
{ "5kc", PROCESSOR_5KC, 64 },
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/mips.h,v
retrieving revision 1.390
diff -c -3 -r1.390 mips.h
*** config/mips/mips.h 27 Apr 2005 09:11:58 -0000 1.390
--- config/mips/mips.h 6 May 2005 15:37:31 -0000
***************
*** 36,41 ****
--- 36,43 ----
PROCESSOR_4KC,
PROCESSOR_5KC,
PROCESSOR_20KC,
+ PROCESSOR_24K,
+ PROCESSOR_24KX,
PROCESSOR_M4K,
PROCESSOR_R3000,
PROCESSOR_R3900,
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/mips.md,v
retrieving revision 1.315
diff -c -3 -r1.315 mips.md
*** config/mips/mips.md 13 Mar 2005 18:03:25 -0000 1.315
--- config/mips/mips.md 6 May 2005 15:37:32 -0000
***************
*** 157,162 ****
--- 157,173 ----
(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
(const_string "unknown"))
+ ;; Mode for conversion types (fcvt)
+ ;; I2S integer to float single (SI/DI to SF)
+ ;; I2D integer to float double (SI/DI to DF)
+ ;; S2I float to integer (SF to SI/DI)
+ ;; D2I float to integer (DF to SI/DI)
+ ;; D2S double to float single
+ ;; S2D float single to double
+
+ (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
+ (const_string "unknown"))
+
;; Is this an extended instruction in mips16 mode?
(define_attr "extended_mips16" "no,yes"
(const_string "no"))
***************
*** 254,260 ****
;; Attribute describing the processor. This attribute must match
exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
!
"default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
--- 265,271 ----
;; Attribute describing the processor. This attribute must match
exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
!
"default,4kc,5kc,20kc,24k,24kx,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
***************
*** 478,483 ****
--- 489,495 ----
(define_cpu_unit "alu" "alu")
(define_cpu_unit "imuldiv" "imuldiv")
+ (include "24k.md")
(include "3000.md")
(include "4000.md")
(include "4100.md")
***************
*** 2130,2135 ****
--- 2142,2148 ----
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.s.d\t%0,%1"
[(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "D2S")
(set_attr "mode" "SF")])
;; Integer truncation patterns. Truncating SImode values to smaller
***************
*** 2444,2449 ****
--- 2457,2463 ----
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.d.s\t%0,%1"
[(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "S2D")
(set_attr "mode" "DF")])
;;
***************
*** 2472,2477 ****
--- 2486,2492 ----
"trunc.w.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "4")])
(define_insn "fix_truncdfsi2_macro"
***************
*** 2487,2492 ****
--- 2502,2508 ----
}
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "36")])
(define_expand "fix_truncsfsi2"
***************
*** 2507,2513 ****
"TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
"trunc.w.s %0,%1"
[(set_attr "type" "fcvt")
! (set_attr "mode" "DF")
(set_attr "length" "4")])
(define_insn "fix_truncsfsi2_macro"
--- 2523,2530 ----
"TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
"trunc.w.s %0,%1"
[(set_attr "type" "fcvt")
! (set_attr "mode" "SF")
! (set_attr "cnv_mode" "S2I")
(set_attr "length" "4")])
(define_insn "fix_truncsfsi2_macro"
***************
*** 2522,2528 ****
return "trunc.w.s %0,%1,%2";
}
[(set_attr "type" "fcvt")
! (set_attr "mode" "DF")
(set_attr "length" "36")])
--- 2539,2546 ----
return "trunc.w.s %0,%1,%2";
}
[(set_attr "type" "fcvt")
! (set_attr "mode" "SF")
! (set_attr "cnv_mode" "S2I")
(set_attr "length" "36")])
***************
*** 2533,2538 ****
--- 2551,2557 ----
"trunc.l.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "4")])
***************
*** 2543,2548 ****
--- 2562,2568 ----
"trunc.l.s %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")
(set_attr "length" "4")])
***************
*** 2553,2558 ****
--- 2573,2579 ----
"cvt.d.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")
(set_attr "length" "4")])
***************
*** 2563,2568 ****
--- 2584,2590 ----
"cvt.d.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")
(set_attr "length" "4")])
***************
*** 2573,2578 ****
--- 2595,2601 ----
"cvt.s.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")
(set_attr "length" "4")])
***************
*** 2583,2588 ****
--- 2606,2612 ----
"cvt.s.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")
(set_attr "length" "4")])
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