[PATCH] adjust dwarf ra column to libexc expectations on mips-irix

[Olivier Hainque]

Hello,

This is a followup to http://gcc.gnu.org/ml/gcc-patches/2005-03/msg01487.html

 GCC for mips currently uses the hard return reg column (31) as the dwarf
 return address column. This badly confuses the system unwinder on IRIX.

 The patch below addresses that by overriding DWARF_FRAME_RETURN_COLUMN on
 IRIX and by adjusting 'mips_frame_set' to note an additional dwarf ra column
 change when r31 is saved and the dwarf ra column number differs.

 Bootstrapped and regression tested on mips-sgi-irix6.4 for languages=all,ada
 and mainline sources from 20050315.

2005-03-27  Olivier Hainque  <hainque@adacore.com>

	* config/mips/iris6.h (DWARF_FRAME_RETURN_COLUMN): Redefine to
	match what the system unwinder expects.
	* config/mips/mips.c (mips_frame_set): If we're saving the return
	address register and the dwarf return address column number differs
	from the hard register number, note the dwarf return address save
	too.

*** config/mips/iris6.h.orig	Mon Feb 28 10:23:38 2005
--- config/mips/iris6.h	Thu Mar 24 17:37:17 2005
*************** Boston, MA 02111-1307, USA.  */
*** 38,43 ****
--- 38,48 ----
     compiling -g.  This guarantees that we can unwind the stack.  */
  #define DWARF2_FRAME_INFO 1
  
+ /* The system unwinder in libexc requires a specific dwarf return address
+    column to work.  */
+ #undef  DWARF_FRAME_RETURN_COLUMN
+ #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
+ 
  #undef MACHINE_TYPE
  #define MACHINE_TYPE "SGI running IRIX 6.x"
  
*** config/mips/mips.c.orig	Wed Mar 16 03:56:42 2005
--- config/mips/mips.c	Thu Mar 24 17:35:41 2005
*************** mips_frame_set (rtx mem, rtx reg)
*** 6277,6282 ****
--- 6277,6298 ----
  {
    rtx set = gen_rtx_SET (VOIDmode, mem, reg);
    RTX_FRAME_RELATED_P (set) = 1;
+ 
+   /* If we're saving the return address register and the dwarf return
+      address column number differs from the hard register number, note
+      the dwarf return address save too.  */
+   if (REGNO (reg) == GP_REG_FIRST + 31
+       && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
+     {
+       rtx ra_column_set
+ 	= gen_rtx_SET (VOIDmode,
+ 		       mem,
+ 		       gen_rtx_REG (word_mode, DWARF_FRAME_RETURN_COLUMN));
+       RTX_FRAME_RELATED_P (ra_column_set) = 1;
+ 
+       set = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, ra_column_set));
+     }
+ 
    return set;
  }