[patch] sparc: Move predicates to predicates.md.

Eric Botcazou ebotcazou@libertysurf.fr
Thu Mar 17 22:58:00 GMT 2005


> Attached is a patch to move predicates to predicates.md.
>
> Built cc1 for sparc-elf.  OK to apply?

That's unfortunate, I started doing it one week ago.  Given that I'm cleaning 
them up in the process, I'd rather finish the work myself.  Sorry.

FWIW preliminary predicates.md attached.

-- 
Eric Botcazou
-------------- next part --------------
;; Predicate definitions for SPARC.
;; Copyright (C) 2005 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

;; Return 1 if OP is the zero constant for MODE.
(define_predicate "zero_operand"
  (and (match_code "const_int,const_double,const_vector")
       (match_test "op == CONST0_RTX (mode)")))

;; Return 1 if OP is the one integral constant.
(define_predicate "one_integral_operand"
  (and (match_code "const_int")
       (match_test "op == const1_rtx")))

;; Return 1 if OP is either the zero constant or a register.
(define_predicate "reg_or_zero_operand"
  (ior (match_operand 0 "register_operand")
       (match_operand 0 "zero_operand")))

;; Return 1 if OP is a register operand in a floating point register.
(define_predicate "fp_reg_operand"
  (match_operand 0 "register_operand")
{
  if (GET_CODE (op) == SUBREG)
    op = SUBREG_REG (op); /* Possibly a MEM */
  return REG_P (op) && SPARC_FP_REG_P (REGNO (op));
})

;; Return 1 if OP is an integer register.
(define_predicate "int_reg_operand"
  (ior (match_test "register_operand (op, SImode)")
       (match_test "TARGET_ARCH64 && register_operand (op, DImode)")))

;; Return 1 if OP is a floating point condition code register.
(define predicate "fcc_reg_operand"
  (match_code "reg")
{
  if (mode != VOIDmode && mode != GET_MODE (op))
    return 0;
  if (mode == VOIDmode
      && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
    return 0;

#if 0 /* ??? 1 when %fcc0-3 are pseudos first.  See gen_compare_reg().  */
  if (reg_renumber == 0)
    return REGNO (op) >= FIRST_PSEUDO_REGISTER;
  return REGNO_OK_FOR_CCFP_P (REGNO (op));
#else
  return ((unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG) < 4;
#endif
}

;; Return 1 if OP is the floating point condition code register fcc0.
(define predicate "fcc_reg_operand"
  (match_code "reg")
{
  if (mode != VOIDmode && mode != GET_MODE (op))
    return 0;
  if (mode == VOIDmode
      && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
    return 0;

  return REGNO (op) == SPARC_FCC_REG;
})

;; Return 1 if OP is an integer or floating point condition code register.
(define_predicate "icc_or_fcc_reg_operand"
  (match_code "reg")
{
  if (REGNO (op) == SPARC_ICC_REG)
    {
      if (mode != VOIDmode && mode != GET_MODE (op))
	return 0;
      if (mode == VOIDmode
	  && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
	return 0;

      return 1;
    }

  return fcc_reg_operand (op, mode);
})

;; Return 1 if OP is an address suitable for a call insn.
(define_predicate "call_operand_address"
  (ior (match_operand 0 "symbolic_operand")
       (match_test "memory_address_p (Pmode, op)"))))

;; Return 1 if OP is an operand suitable for a call insn.
(define_predicate "call_operand"
  (and (match_code "mem")
       (match_test "call_operand_address (XEXP (op, 0), mode)")))


{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}},			\
{"symbolic_memory_operand", {SUBREG, MEM}},				\
{"label_ref_operand", {LABEL_REF}},					\
{"sp64_medium_pic_operand", {CONST}},					\
{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}},			\
{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}},		\
{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}},			\
{"splittable_symbolic_memory_operand", {MEM}},				\
{"splittable_immediate_memory_operand", {MEM}},				\
{"eq_or_neq", {EQ, NE}},						\
{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}},			\
{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}},	\
{"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}},	\
{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}},				\
{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}},				\
{"cc_arithop", {AND, IOR, XOR}},					\
{"cc_arithopn", {AND, IOR}},						\
{"arith_operand", {SUBREG, REG, CONST_INT}},				\
{"arith_add_operand", {SUBREG, REG, CONST_INT}},			\
{"arith11_operand", {SUBREG, REG, CONST_INT}},				\
{"arith10_operand", {SUBREG, REG, CONST_INT}},				\
{"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
{"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
{"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
{"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
{"small_int", {CONST_INT}},						\
{"small_int_or_double", {CONST_INT, CONST_DOUBLE}},			\
{"uns_small_int", {CONST_INT}},						\
{"uns_arith_operand", {SUBREG, REG, CONST_INT}},			\
{"clobbered_register", {REG}},						\
{"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}},		\
{"compare_operand", {SUBREG, REG, ZERO_EXTRACT}},			\
{"const64_operand", {CONST_INT, CONST_DOUBLE}},				\
{"const64_high_operand", {CONST_INT, CONST_DOUBLE}},			\
{"tgd_symbolic_operand", {SYMBOL_REF}},					\
{"tld_symbolic_operand", {SYMBOL_REF}},					\
{"tie_symbolic_operand", {SYMBOL_REF}},					\
{"tle_symbolic_operand", {SYMBOL_REF}},


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