ia64: replace zxt4 with addp6
Jan Beulich
JBeulich@novell.com
Mon Jan 10 16:54:00 GMT 2005
>> +(define_insn "*shladdp4_internal"
>> + [(set (match_operand:DI 0 "gr_register_operand" "=r")
>> + (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand"
>> "r")
>> + (match_operand:DI 2 "const_int_operand"
>> "n"))
>> + (match_operand:DI 3 "const_int_operand" "n")))]
>> + "EXTRA_CONSTRAINT (operands[2], 'R')
>
>I would prefer that you create a shladd_log2_operand for this.
>But otherwise this is a nice improvement as well.
Here we go.
Bootstrapped and tested on ia64-unknown-linux-gnu.
Jan
gcc/
2005-01-10 Jan Beulich <jbeulich@novell.com>
* config/ia64/ia64.md (zero_extendsidi2): Replace zxt4 by
addp4.
Change respective itanium_class attribute to ialu.
(shladdp4_internal): New.
* config/ia64/predicates.md (shladd_log2_operand): New.
---
/home/jbeulich/src/gcc/mainline/2005-01-06.13.34/gcc/config/ia64/ia64.md 2005-01-04
09:22:55.000000000 +0100
+++ 2005-01-06.13.34/gcc/config/ia64/ia64.md 2005-01-10
12:45:03.544786734 +0100
@@ -866,10 +866,10 @@
(match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
""
"@
- zxt4 %0 = %1
+ addp4 %0 = %1, r0
ld4%O1 %0 = %1%P1
fmix.r %0 = f0, %1"
- [(set_attr "itanium_class" "xtd,ld,fmisc")])
+ [(set_attr "itanium_class" "ialu,ld,fmisc")])
;; Convert between floating point types of different sizes.
@@ -1138,6 +1138,15 @@
[(set_attr "itanium_class" "ishf")])
;; Combine doesn't like to create bit-field insertions into zero.
+(define_insn "*shladdp4_internal"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand"
"r")
+ (match_operand:DI 2 "shladd_log2_operand"
"n"))
+ (match_operand:DI 3 "const_int_operand" "n")))]
+ "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL
(operands[2]) == 32"
+ "shladdp4 %0 = %1, %2, r0"
+ [(set_attr "itanium_class" "ialu")])
+
(define_insn "*depz_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand"
"r")
---
/home/jbeulich/src/gcc/mainline/2005-01-06.13.34/gcc/config/ia64/predicates.md 2005-01-04
09:22:55.000000000 +0100
+++ 2005-01-06.13.34/gcc/config/ia64/predicates.md 2005-01-10
13:26:16.698076750 +0100
@@ -312,6 +312,11 @@
(match_test "INTVAL (op) == 2 || INTVAL (op) == 4 ||
INTVAL (op) == 8 || INTVAL (op) == 16")))
+;; True if OP is one of the immediate values 1, 2, 3, or 4.
+(define_predicate "shladd_log2_operand"
+ (and (match_code "const_int")
+ (match_test "INTVAL (op) >= 1 && INTVAL (op) <= 4")))
+
;; True if OP is one of the immediate values -16, -8, -4, -1, 1, 4,
8, 16.
(define_predicate "fetchadd_operand"
(and (match_code "const_int")
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: gcc-mainline-ia64-addp4zxt.patch
URL: <http://gcc.gnu.org/pipermail/gcc-patches/attachments/20050110/4137502b/attachment.ksh>
More information about the Gcc-patches
mailing list