ia64: replace zxt4 with addp6
Jan Beulich
JBeulich@novell.com
Fri Jan 7 14:10:00 GMT 2005
This replaces zxt4, which can only be executed on I-units, by addp4
(usable
on both I- and M-units), allowing tighter code to be generated.
Similarly,
this adds an shladdp4 insn replacing dep.z (which can be executed only
on
I0) when possible.
Bootstrapped and tested on ia64-unknown-linux-gnu.
Jan
gcc/
2005-01-06 Jan Beulich <jbeulich@novell.com>
* config/ia64/ia64.md (zero_extendsidi2): Replace zxt4 by
addp4.
Change respective itanium_class attribute to ialu.
(shladdp4_internal): New.
---
/home/jbeulich/src/gcc/mainline/2005-01-06.13.34/gcc/config/ia64/ia64.md 2005-01-04
09:22:55.000000000 +0100
+++ 2005-01-06.13.34/gcc/config/ia64/ia64.md 2005-01-07
08:32:25.649162389 +0100
@@ -866,10 +866,10 @@
(match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
""
"@
- zxt4 %0 = %1
+ addp4 %0 = %1, r0
ld4%O1 %0 = %1%P1
fmix.r %0 = f0, %1"
- [(set_attr "itanium_class" "xtd,ld,fmisc")])
+ [(set_attr "itanium_class" "ialu,ld,fmisc")])
;; Convert between floating point types of different sizes.
@@ -1138,6 +1138,16 @@
[(set_attr "itanium_class" "ishf")])
;; Combine doesn't like to create bit-field insertions into zero.
+(define_insn "*shladdp4_internal"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand"
"r")
+ (match_operand:DI 2 "const_int_operand"
"n"))
+ (match_operand:DI 3 "const_int_operand" "n")))]
+ "EXTRA_CONSTRAINT (operands[2], 'R')
+ && ia64_depz_field_mask (operands[3], operands[2]) + INTVAL
(operands[2]) == 32"
+ "shladdp4 %0 = %1, %2, r0"
+ [(set_attr "itanium_class" "ialu")])
+
(define_insn "*depz_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand"
"r")
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