[patch] S/390: cleanup machine description (3/3)
Adrian Straetling
straetling@de.ibm.com
Wed Dec 14 12:51:00 GMT 2005
On Wed, Dec 14, 2005 at 01:20:57PM +0100, Adrian Straetling wrote:
> Hi,
>
> this little series of patches performs some cleanup that is waiting on
> my disk for some time now.
>
> All bootstrap fine and regtest without regressions.
this patch combines several shift patterns that have two operands on 31-
and three on 64-bit machines.
2005-12-14 Adrian Straetling <straetling@de.ibm.com>
* gcc/config/s390/s390.md ("d0","1"): New mode attributes.
("<shift>di3","<shift>si3"): Merge.
("*<shift>di3_and","*<shift>si3_and"): Merge.
("ashrdi3","ashrsi3"): Merge.
("*ashrdi3_cc","*ashrsi3_cc"): Merge.
("*ashrdi3_cc_and","*ashrsi3_cc_and"): Merge.
("*ashrdi3_cconly","*ashrsi3_cconly"): Merge.
("*ashrdi3_cconly_and","*ashrsi3_cconly_and"): Merge.
("*ashrdi3","*ashrsi3"): Merge.
("*ashrdi3_and","*ashrsi3_and"): Merge.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig 2005-12-13 12:36:55.796521831 +0100
--- gcc/config/s390/s390.md 2005-12-13 12:38:19.286521831 +0100
*************** (define_mode_attr de [(DF "d") (SF "e")]
*** 299,304 ****
--- 299,314 ----
;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
(define_mode_attr dee [(DF "d") (SF "ee")])
+ ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
+ ;; and "0" in SImode. This allows to combine instructions of which the 31bit
+ ;; version only operates on one register.
+ (define_mode_attr d0 [(DI "d") (SI "0")])
+
+ ;; In combination with d0 this allows to combine instructions of which the 31bit
+ ;; version only operates on one register. The DImode version needs an additional
+ ;; register for the assembler output.
+ (define_mode_attr 1 [(DI "%1,") (SI "")])
+
;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
;; 'ashift' and "srdl" in 'lshiftrt'.
(define_code_attr lr [(ashift "l") (lshiftrt "r")])
*************** (define_insn "*rotl<mode>3_and"
*** 6250,6262 ****
;;
;
! ; (ashl|lshr)di3 instruction pattern(s).
;
! (define_expand "<shift>di3"
! [(set (match_operand:DI 0 "register_operand" "")
! (SHIFT:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
""
"")
--- 6260,6272 ----
;;
;
! ; (ashl|lshr)(di|si)3 instruction pattern(s).
;
! (define_expand "<shift><mode>3"
! [(set (match_operand:DSI 0 "register_operand" "")
! (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
""
"")
*************** (define_insn "*<shift>di3_31"
*** 6269,6281 ****
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*<shift>di3_64"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
! "TARGET_64BIT"
! "s<lr>lg\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
(define_insn "*<shift>di3_31_and"
--- 6279,6291 ----
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*<shift><mode>3"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
! ""
! "s<lr>l<g>\t%0,<1>%Y2"
! [(set_attr "op_type" "RS<E>")
(set_attr "atype" "reg")])
(define_insn "*<shift>di3_31_and"
*************** (define_insn "*<shift>di3_31_and"
*** 6288,6312 ****
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*<shift>di3_64_and"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n"))))]
! "TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
! "s<lr>lg\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
;
! ; ashrdi3 instruction pattern(s).
;
! (define_expand "ashrdi3"
[(parallel
! [(set (match_operand:DI 0 "register_operand" "")
! (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
--- 6298,6322 ----
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*<shift><mode>3_and"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n"))))]
! "(INTVAL (operands[3]) & 63) == 63"
! "s<lr>l<g>\t%0,<1>%Y2"
! [(set_attr "op_type" "RS<E>")
(set_attr "atype" "reg")])
;
! ; ashr(di|si)3 instruction pattern(s).
;
! (define_expand "ashr<mode>3"
[(parallel
! [(set (match_operand:DSI 0 "register_operand" "")
! (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
*************** (define_insn "*ashrdi3_31"
*** 6344,6380 ****
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*ashrdi3_cc_64"
[(set (reg CC_REGNUM)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d")
! (ashiftrt:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
! "srag\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
! (define_insn "*ashrdi3_cconly_64"
[(set (reg CC_REGNUM)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0)))
! (clobber (match_scratch:DI 0 "=d"))]
! "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
! "srag\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
! (define_insn "*ashrdi3_64"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
! "srag\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
--- 6354,6390 ----
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*ashr<mode>3_cc"
[(set (reg CC_REGNUM)
! (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0)))
! (set (match_operand:GPR 0 "register_operand" "=d")
! (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCSmode)"
! "sra<g>\t%0,<1>%Y2"
! [(set_attr "op_type" "RS<E>")
(set_attr "atype" "reg")])
! (define_insn "*ashr<mode>3_cconly"
[(set (reg CC_REGNUM)
! (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0)))
! (clobber (match_scratch:GPR 0 "=d"))]
! "s390_match_ccmode(insn, CCSmode)"
! "sra<g>\t%0,<1>%Y2"
! [(set_attr "op_type" "RS<E>")
(set_attr "atype" "reg")])
! (define_insn "*ashr<mode>3"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
(clobber (reg:CC CC_REGNUM))]
! ""
! "sra<g>\t%0,<1>%Y2"
! [(set_attr "op_type" "RS<E>")
(set_attr "atype" "reg")])
*************** (define_insn "*ashrdi3_31_and"
*** 6418,6559 ****
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*ashrdi3_cc_64_and"
[(set (reg CC_REGNUM)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n")))
(const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d")
! (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
! "TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
! && (INTVAL (operands[3]) & 63) == 63"
! "srag\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
!
! (define_insn "*ashrdi3_cconly_64_and"
! [(set (reg CC_REGNUM)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n")))
! (const_int 0)))
! (clobber (match_scratch:DI 0 "=d"))]
! "TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
! && (INTVAL (operands[3]) & 63) == 63"
! "srag\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
!
! (define_insn "*ashrdi3_64_and"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n"))))
! (clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
! "srag\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
!
! ;
! ; (ashl|lshr)si3 instruction pattern(s).
! ;
!
! (define_insn "<shift>si3"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
! ""
! "s<lr>l\t%0,%Y2"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
!
! (define_insn "*<shift>si3_and"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n"))))]
! "(INTVAL (operands[3]) & 63) == 63"
! "s<lr>l\t%0,%Y2"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
!
! ;
! ; ashrsi3 instruction pattern(s).
! ;
!
! (define_insn "*ashrsi3_cc"
! [(set (reg CC_REGNUM)
! (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
! (const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d")
! (ashiftrt:SI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCSmode)"
! "sra\t%0,%Y2"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
!
!
! (define_insn "*ashrsi3_cconly"
! [(set (reg CC_REGNUM)
! (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
! (const_int 0)))
! (clobber (match_scratch:SI 0 "=d"))]
! "s390_match_ccmode(insn, CCSmode)"
! "sra\t%0,%Y2"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
!
! (define_insn "ashrsi3"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
! (clobber (reg:CC CC_REGNUM))]
! ""
! "sra\t%0,%Y2"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
!
! ; with implicit ANDs
!
! (define_insn "*ashrsi3_cc_and"
! [(set (reg CC_REGNUM)
! (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n")))
! (const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d")
! (ashiftrt:SI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
! "sra\t%0,%Y2"
! [(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
!
! (define_insn "*ashrsi3_cconly_and"
[(set (reg CC_REGNUM)
! (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n")))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d"))]
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
! "sra\t%0,%Y2"
! [(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*ashrsi3_and"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n"))))
(clobber (reg:CC CC_REGNUM))]
"(INTVAL (operands[3]) & 63) == 63"
! "sra\t%0,%Y2"
! [(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 6428,6467 ----
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*ashr<mode>3_cc_and"
[(set (reg CC_REGNUM)
! (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n")))
(const_int 0)))
! (set (match_operand:GPR 0 "register_operand" "=d")
! (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
! "sra<g>\t%0,<1>%Y2"
! [(set_attr "op_type" "RS<E>")
(set_attr "atype" "reg")])
! (define_insn "*ashr<mode>3_cconly_and"
[(set (reg CC_REGNUM)
! (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n")))
(const_int 0)))
! (clobber (match_scratch:GPR 0 "=d"))]
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
! "sra<g>\t%0,<1>%Y2"
! [(set_attr "op_type" "RS<E>")
(set_attr "atype" "reg")])
! (define_insn "*ashr<mode>3_and"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
! (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
! (match_operand:SI 3 "const_int_operand" "n"))))
(clobber (reg:CC CC_REGNUM))]
"(INTVAL (operands[3]) & 63) == 63"
! "sra<g>\t%0,<1>%Y2"
! [(set_attr "op_type" "RS<E>")
(set_attr "atype" "reg")])
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