[patch] Fix behavior of TER on unrolled loops

[David Edelsohn]

>>>>> Zdenek writes:

Zdenek> IMO this is the only way that can work well on architecture that
Zdenek> has small number of registers and simultaneously rich addressing modes
Zdenek> (i.e., x86).

	x86 has a small number of user-ISA-defined registers, but the
microarchitecture of current implementations has many more internal
registers.  Targeting the microarchitecture has proven to be very
effective for other high-performance x86 compilers.  Internally, current
x86 processors are RISC-like.

Zdenek> I find it more senseful to make a simple pass (SR) more clever, than
Zdenek> making the task that is already almost impossible to solve as it is (RA)
Zdenek> more complex.

	SR occurs too early to have an accurate model of register pressure
and to infer the final instructions that will be produced.  Tuning and
maintaining the heuristics and the register pressure information for every
future change to GCC's optimization information is an unnecessary and
unproductive burden.

	The consensus among GCC developers is toward light-weight,
narrowly-defined optimization passes, including later passes to
reconstitute loops or complicated addressing modes to match target
dependencies based upon more accurate information.

	You seem to have a different mental model of the optimization
design for GCC than most other GCC developers.  The fundamental
disagreement is that you have a different premise than most other GCC
developers and with the way that GCC development is headed.  As long as
the assumptions do not match, the discussion of the implementation details
is going to clash.

David