[PATCH, committed] PowerPC LTU and GTU SCC compare patterns
David Edelsohn
dje@watson.ibm.com
Thu Aug 18 16:44:00 GMT 2005
This patch converts LTU and GTU SCC patterns that perform compare
to use define_insn_and_split to allow better scheduling of the final
instruction.
Bootstrapped and regression tested on powerpc-ibm-aix5.2.0.0
David
* config/rs6000/rs6000.md (ltu<mode>_compare): Convert to
define_insn_and_split.
(plus_ltu<mode>_compare): Same.
(gtu<mode>_compare): Same.
(plus_gtu<mode>_compare): Same.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.398
diff -c -p -r1.398 rs6000.md
*** rs6000.md 17 Aug 2005 23:12:16 -0000 1.398
--- rs6000.md 18 Aug 2005 14:00:33 -0000
***************
*** 11995,12001 ****
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
! (define_insn "*ltu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
--- 11995,12001 ----
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
! (define_insn_and_split "*ltu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
***************
*** 12004,12038 ****
(set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
(ltu:P (match_dup 1) (match_dup 2)))]
""
! "@
! {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
! {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
! #
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "12,12,16,16")])
!
! (define_split
! [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (ltu:P (match_operand:P 1 "gpc_reg_operand" "")
! (match_operand:P 2 "reg_or_neg_short_operand" ""))
! (const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "")
! (ltu:P (match_dup 1) (match_dup 2)))]
! "reload_completed"
! [(set (match_dup 0)
! (ltu:P (match_dup 1) (match_dup 2)))
! (set (match_dup 3)
! (compare:CC (match_dup 0)
! (const_int 0)))]
"")
(define_insn_and_split "*plus_ltu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
(plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
""
"#"
"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
--- 12004,12022 ----
(set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
(ltu:P (match_dup 1) (match_dup 2)))]
""
! "#"
! ""
! [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
! (parallel [(set (match_dup 3)
! (compare:CC (neg:P (match_dup 0)) (const_int 0)))
! (set (match_dup 0) (neg:P (match_dup 0)))])]
"")
(define_insn_and_split "*plus_ltu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
(plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
""
"#"
"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
***************
*** 12040,12112 ****
(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
"")
! (define_insn ""
! [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
! (compare:CC
! (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
! (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
! (const_int 0)))
! (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
! "TARGET_32BIT"
! "@
! {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
! {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
! #
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "12,12,16,16")])
!
! (define_split
! [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "reg_or_neg_short_operand" ""))
! (match_operand:SI 3 "gpc_reg_operand" ""))
! (const_int 0)))
! (clobber (match_scratch:SI 4 ""))]
! "TARGET_32BIT && reload_completed"
! [(set (match_dup 4)
! (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
! (match_dup 3)))
! (set (match_dup 0)
! (compare:CC (match_dup 4)
! (const_int 0)))]
! "")
!
! (define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
! (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
! (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
! (const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
! (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
! "TARGET_32BIT"
! "@
! {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
! {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
! #
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "12,12,16,16")])
!
! (define_split
! [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "reg_or_neg_short_operand" ""))
! (match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "")
! (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
! "TARGET_32BIT && reload_completed"
! [(set (match_dup 0)
! (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
! (set (match_dup 4)
! (compare:CC (match_dup 0)
! (const_int 0)))]
"")
(define_insn "*neg_ltu<mode>"
--- 12024,12046 ----
(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
"")
! (define_insn_and_split "*plus_ltu<mode>_compare"
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
! (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
! (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
! (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
! ""
! "#"
! "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
! [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
! (parallel [(set (match_dup 4)
! (compare:CC (minus:P (match_dup 3) (match_dup 0))
! (const_int 0)))
! (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
"")
(define_insn "*neg_ltu<mode>"
***************
*** 12799,12805 ****
(const_int 0)))]
"")
! (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))))]
--- 12733,12739 ----
(const_int 0)))]
"")
! (define_insn "*neg_gt0si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))))]
***************
*** 12808,12814 ****
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 0))))]
--- 12742,12748 ----
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn "neg_gt0di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 0))))]
***************
*** 12836,12842 ****
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
! (define_insn "*gtu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC
(gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
--- 12770,12776 ----
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
! (define_insn_and_split "*gtu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC
(gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
***************
*** 12845,12873 ****
(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(gtu:P (match_dup 1) (match_dup 2)))]
""
! "@
! {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "12,16")])
!
! (define_split
! [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (gtu:P (match_operand:P 1 "gpc_reg_operand" "")
! (match_operand:P 2 "reg_or_short_operand" ""))
! (const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "")
! (gtu:P (match_dup 1) (match_dup 2)))]
! "reload_completed"
! [(set (match_dup 0)
! (gtu:P (match_dup 1) (match_dup 2)))
! (set (match_dup 3)
! (compare:CC (match_dup 0)
! (const_int 0)))]
"")
! (define_insn_and_split "plus_gtu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=&r")
(plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "reg_or_short_operand" "rI"))
--- 12779,12793 ----
(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(gtu:P (match_dup 1) (match_dup 2)))]
""
! "#"
! ""
! [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
! (parallel [(set (match_dup 3)
! (compare:CC (neg:P (match_dup 0)) (const_int 0)))
! (set (match_dup 0) (neg:P (match_dup 0)))])]
"")
! (define_insn_and_split "*plus_gtu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=&r")
(plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "reg_or_short_operand" "rI"))
***************
*** 12879,13020 ****
(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
"")
! (define_insn ""
! [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
! (compare:CC
! (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
! (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
! (const_int 0)))
! (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
! "TARGET_32BIT"
! "@
! {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
! {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
! #
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "8,12,12,16")])
!
! (define_split
! [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "reg_or_short_operand" ""))
! (match_operand:SI 3 "gpc_reg_operand" ""))
! (const_int 0)))
! (clobber (match_scratch:SI 4 ""))]
! "TARGET_32BIT && reload_completed"
! [(set (match_dup 4)
! (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
! (match_dup 3)))
! (set (match_dup 0)
! (compare:CC (match_dup 4)
! (const_int 0)))]
! "")
!
! (define_insn ""
! [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
! (compare:CC
! (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
! (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
! (const_int 0)))
! (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
! "TARGET_64BIT"
! "@
! addic %4,%1,%k2\;addze. %4,%3
! subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
! #
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "8,12,12,16")])
!
! (define_split
! [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
! (match_operand:DI 2 "reg_or_short_operand" ""))
! (match_operand:DI 3 "gpc_reg_operand" ""))
! (const_int 0)))
! (clobber (match_scratch:DI 4 ""))]
! "TARGET_64BIT && reload_completed"
! [(set (match_dup 4)
! (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
! (match_dup 3)))
! (set (match_dup 0)
! (compare:CC (match_dup 4)
! (const_int 0)))]
! "")
!
! (define_insn ""
! [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
! (compare:CC
! (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
! (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
! (const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
! (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
! "TARGET_32BIT"
! "@
! {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
! {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
! #
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "8,12,12,16")])
!
! (define_split
! [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "reg_or_short_operand" ""))
! (match_operand:SI 3 "gpc_reg_operand" ""))
! (const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "")
! (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
! "TARGET_32BIT && reload_completed"
! [(set (match_dup 0)
! (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
! (set (match_dup 4)
! (compare:CC (match_dup 0)
! (const_int 0)))]
! "")
!
! (define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
! (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
! (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
! (const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
! (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
! "TARGET_64BIT"
! "@
! addic %0,%1,%k2\;addze. %0,%3
! subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
! #
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "8,12,12,16")])
!
! (define_split
! [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
! (match_operand:DI 2 "reg_or_short_operand" ""))
! (match_operand:DI 3 "gpc_reg_operand" ""))
(const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "")
! (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
! "TARGET_64BIT && reload_completed"
! [(set (match_dup 0)
! (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
! (set (match_dup 4)
! (compare:CC (match_dup 0)
! (const_int 0)))]
"")
(define_insn "*neg_gtu<mode>"
--- 12799,12821 ----
(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
"")
! (define_insn_and_split "*plus_gtu<mode>_compare"
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
! (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
! (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
! (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
! ""
! "#"
! "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
! [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
! (parallel [(set (match_dup 4)
! (compare:CC (minus:P (match_dup 3) (match_dup 0))
! (const_int 0)))
! (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
"")
(define_insn "*neg_gtu<mode>"
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