[PATCH, committed] More PowerPC SCC patterns converted to mode macros
David Edelsohn
dje@watson.ibm.com
Wed Aug 17 23:29:00 GMT 2005
Bootstrapped and regression tested on powerpc-ibm-aix5.2.0.0
David
* config/rs6000/rs6000.md (leu<mode>): Convert to mode macro.
(leu<mode>_compare): Same.
(plus_leu<mode>): Same.
(neg_leu<mode>): Same.
(and_neg_leu<mode): Same.
(ltu<mode>_compare): Same.
(plus_ltu<mode>): Same.
(geu<mode>): Same.
(geu<mode>_compare): Same.
(plus_geu<mode>): Same.
(neg_geu<mode>): Same.
(and_neg_geu<mode>): Same.
(plus_gt<mode>): Same.
(gtu<mode>_compare): Same.
(plus_gtu<mode>): Same.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.397
diff -c -p -r1.397 rs6000.md
*** rs6000.md 16 Aug 2005 15:13:40 -0000 1.397
--- rs6000.md 17 Aug 2005 14:44:18 -0000
***************
*** 11658,11721 ****
{ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (match_operand:SI 2 "reg_or_short_operand" "rI")))]
! "TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn ""
! [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
! (match_operand:DI 2 "reg_or_short_operand" "rI")))]
! "TARGET_64BIT"
! "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
!
! (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC
! (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
! (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
(const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
! (leu:DI (match_dup 1) (match_dup 2)))]
! "TARGET_64BIT"
! "@
! subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "12,16")])
!
! (define_split
! [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
! (match_operand:DI 2 "reg_or_short_operand" ""))
! (const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "")
! (leu:DI (match_dup 1) (match_dup 2)))]
! "TARGET_64BIT && reload_completed"
! [(set (match_dup 0)
! (leu:DI (match_dup 1) (match_dup 2)))
! (set (match_dup 3)
! (compare:CC (match_dup 0)
! (const_int 0)))]
! "")
!
! (define_insn ""
! [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
! (compare:CC
! (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
! (const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! (leu:SI (match_dup 1) (match_dup 2)))]
! "TARGET_32BIT"
"@
{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
#"
--- 11658,11681 ----
{ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
! (define_insn "*leu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=r")
! (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
! (match_operand:P 2 "reg_or_short_operand" "rI")))]
! ""
"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn "*leu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC
! (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
! (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
! (leu:P (match_dup 1) (match_dup 2)))]
! ""
"@
{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
#"
***************
*** 11725,11749 ****
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
! (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "reg_or_short_operand" ""))
(const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "")
! (leu:SI (match_dup 1) (match_dup 2)))]
! "TARGET_32BIT && reload_completed"
[(set (match_dup 0)
! (leu:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
! (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (match_operand:SI 2 "reg_or_short_operand" "rI"))
! (match_operand:SI 3 "gpc_reg_operand" "r")))]
! "TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
[(set_attr "type" "two")
(set_attr "length" "8")])
--- 11685,11709 ----
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
! (leu:P (match_operand:P 1 "gpc_reg_operand" "")
! (match_operand:P 2 "reg_or_short_operand" ""))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "")
! (leu:P (match_dup 1) (match_dup 2)))]
! "reload_completed"
[(set (match_dup 0)
! (leu:P (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
! (define_insn "*plus_leu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
! (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
! (match_operand:P 2 "reg_or_short_operand" "rI"))
! (match_operand:P 3 "gpc_reg_operand" "r")))]
! ""
"{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
[(set_attr "type" "two")
(set_attr "length" "8")])
***************
*** 11813,11834 ****
(const_int 0)))]
"")
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
! "TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
! (and:SI (neg:SI
! (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (match_operand:SI 2 "reg_or_short_operand" "rI")))
! (match_operand:SI 3 "gpc_reg_operand" "r")))]
! "TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
--- 11773,11794 ----
(const_int 0)))]
"")
! (define_insn "*neg_leu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=r")
! (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
! (match_operand:P 2 "reg_or_short_operand" "rI"))))]
! ""
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn "*and_neg_leu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
! (and:P (neg:P
! (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
! (match_operand:P 2 "reg_or_short_operand" "rI")))
! (match_operand:P 3 "gpc_reg_operand" "r")))]
! ""
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
***************
*** 12035,12049 ****
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
! (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
! (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
(const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
! (ltu:SI (match_dup 1) (match_dup 2)))]
! "TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
--- 11995,12009 ----
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
! (define_insn "*ltu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
! (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
! (ltu:P (match_dup 1) (match_dup 2)))]
! ""
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
***************
*** 12055,12095 ****
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
! (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "reg_or_neg_short_operand" ""))
(const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "")
! (ltu:SI (match_dup 1) (match_dup 2)))]
! "TARGET_32BIT && reload_completed"
[(set (match_dup 0)
! (ltu:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
! (define_insn_and_split ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
! (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
! "TARGET_32BIT"
! "#"
! "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
! [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
! "")
!
! (define_insn_and_split ""
! [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
! (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
! (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
! "TARGET_64BIT"
"#"
"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
! [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
"")
(define_insn ""
--- 12015,12043 ----
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
! (ltu:P (match_operand:P 1 "gpc_reg_operand" "")
! (match_operand:P 2 "reg_or_neg_short_operand" ""))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "")
! (ltu:P (match_dup 1) (match_dup 2)))]
! "reload_completed"
[(set (match_dup 0)
! (ltu:P (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
! (define_insn_and_split "*plus_ltu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
! (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
! (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
! ""
"#"
"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
! [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
"")
(define_insn ""
***************
*** 12297,12333 ****
"doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12")])
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
! "TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn ""
! [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
! (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
! (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
! "TARGET_64BIT"
! "@
! subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
! addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
!
! (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
! (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
(const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
! (geu:SI (match_dup 1) (match_dup 2)))]
! "TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
--- 12245,12270 ----
"doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12")])
! (define_insn "*geu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
! (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
! (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
! ""
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn "*geu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC
! (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
! (geu:P (match_dup 1) (match_dup 2)))]
! ""
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
***************
*** 12339,12396 ****
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
! (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "reg_or_neg_short_operand" ""))
! (const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "")
! (geu:SI (match_dup 1) (match_dup 2)))]
! "TARGET_32BIT && reload_completed"
! [(set (match_dup 0)
! (geu:SI (match_dup 1) (match_dup 2)))
! (set (match_dup 3)
! (compare:CC (match_dup 0)
! (const_int 0)))]
! "")
!
! (define_insn ""
! [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
! (compare:CC
! (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
! (const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
! (geu:DI (match_dup 1) (match_dup 2)))]
! "TARGET_64BIT"
! "@
! subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
! addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
! #
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "12,12,16,16")])
!
! (define_split
! [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
! (match_operand:DI 2 "reg_or_neg_short_operand" ""))
(const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "")
! (geu:DI (match_dup 1) (match_dup 2)))]
! "TARGET_64BIT && reload_completed"
[(set (match_dup 0)
! (geu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
! (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
! "TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
{ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
--- 12276,12300 ----
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
! (geu:P (match_operand:P 1 "gpc_reg_operand" "")
! (match_operand:P 2 "reg_or_neg_short_operand" ""))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "")
! (geu:P (match_dup 1) (match_dup 2)))]
! "reload_completed"
[(set (match_dup 0)
! (geu:P (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
! (define_insn "*plus_geu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
! (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
! (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:P 3 "gpc_reg_operand" "r,r")))]
! ""
"@
{sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
{ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
***************
*** 12466,12489 ****
(const_int 0)))]
"")
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
! "TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
{sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
! (and:SI (neg:SI
! (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
! (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
! "TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
--- 12370,12393 ----
(const_int 0)))]
"")
! (define_insn "*neg_geu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
! (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
! (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
! ""
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
{sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn "*and_neg_geu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
! (and:P (neg:P
! (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
! (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
! (match_operand:P 3 "gpc_reg_operand" "r,r")))]
! ""
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
***************
*** 12563,12569 ****
(const_int 0)))]
"")
! (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0)))]
--- 12467,12473 ----
(const_int 0)))]
"")
! (define_insn "*gt0si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0)))]
***************
*** 12572,12578 ****
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 0)))]
--- 12476,12482 ----
[(set_attr "type" "three")
(set_attr "length" "12")])
! (define_insn "*gt0di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 0)))]
***************
*** 12682,12708 ****
(const_int 0)))]
"")
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
! (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (const_int 0))
! (match_operand:SI 2 "gpc_reg_operand" "r")))]
! "TARGET_32BIT"
"{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (const_int 0))
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
- "TARGET_64BIT"
- "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
- [(set_attr "type" "three")
- (set_attr "length" "12")])
-
- (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC
(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
--- 12586,12602 ----
(const_int 0)))]
"")
! (define_insn "*plus_gt<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
! (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
! (const_int 0))
! (match_operand:P 2 "gpc_reg_operand" "r")))]
! ""
"{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC
(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
***************
*** 12942,12956 ****
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
! (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC
! (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
(const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! (gtu:SI (match_dup 1) (match_dup 2)))]
! "TARGET_32BIT"
"@
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
#"
--- 12836,12850 ----
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
! (define_insn "*gtu<mode>_compare"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC
! (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
! (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
! (gtu:P (match_dup 1) (match_dup 2)))]
! ""
"@
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
#"
***************
*** 12960,13031 ****
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
! (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "reg_or_short_operand" ""))
(const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "")
! (gtu:SI (match_dup 1) (match_dup 2)))]
! "TARGET_32BIT && reload_completed"
! [(set (match_dup 0)
! (gtu:SI (match_dup 1) (match_dup 2)))
! (set (match_dup 3)
! (compare:CC (match_dup 0)
! (const_int 0)))]
! "")
!
! (define_insn ""
! [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
! (compare:CC
! (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
! (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
! (const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
! (gtu:DI (match_dup 1) (match_dup 2)))]
! "TARGET_64BIT"
! "@
! subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
! #"
! [(set_attr "type" "compare")
! (set_attr "length" "12,16")])
!
! (define_split
! [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
! (compare:CC
! (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
! (match_operand:DI 2 "reg_or_short_operand" ""))
! (const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "")
! (gtu:DI (match_dup 1) (match_dup 2)))]
! "TARGET_64BIT && reload_completed"
[(set (match_dup 0)
! (gtu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
! (define_insn_and_split ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
! (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (match_operand:SI 2 "reg_or_short_operand" "rI"))
! (match_operand:SI 3 "reg_or_short_operand" "rI")))]
! "TARGET_32BIT"
! "#"
! "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
! [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
! "")
!
! (define_insn_and_split ""
! [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
! (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
! (match_operand:DI 2 "reg_or_short_operand" "rI"))
! (match_operand:DI 3 "reg_or_short_operand" "rI")))]
! "TARGET_64BIT"
"#"
"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
! [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
"")
(define_insn ""
--- 12854,12882 ----
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC
! (gtu:P (match_operand:P 1 "gpc_reg_operand" "")
! (match_operand:P 2 "reg_or_short_operand" ""))
(const_int 0)))
! (set (match_operand:P 0 "gpc_reg_operand" "")
! (gtu:P (match_dup 1) (match_dup 2)))]
! "reload_completed"
[(set (match_dup 0)
! (gtu:P (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
! (define_insn_and_split "plus_gtu<mode>"
! [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
! (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
! (match_operand:P 2 "reg_or_short_operand" "rI"))
! (match_operand:P 3 "reg_or_short_operand" "rI")))]
! ""
"#"
"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
! [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
"")
(define_insn ""
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