[PATCH] Generic vectors 3/3

[Dorit Naishlos]

Paolo Bonzini <paolo.bonzini@lu.unisi.ch> wrote on 14/04/2005 09:33:59:
> >>The patch fixes vect-82.c and vect-83.c (vectorizing the initialization
> >>of an array of long longs).  They failed because the vectorizer didn't
> >>find a 128-bit vector mode for long longs, but now it finds TImode and
> >>uses it to produce vectorized code.
> >>
> >does it use SIMD or "generic" to vectorize these tests? cause unless you
> >use real vector registers you can't support 128-bit so this will get
> >lowered back to long long after vectorization. Is that what's happening
> >here? if so - why vectorize if TImode is not really supported?
> >
> >
> it uses SIMD registers in TImode -- which is supported "enough" to
> vectorize vect-82.c and vect-83.c.  It would not do anything to
> vectorize addition of long longs, because only two of them fit in a
> TImode register.
>

I'm looking at the code generated for these tests (on powerpc-apple-darwin)
and it doesn't look like we're using SIMD registers. But it might be the
rs6000/altivec backend fault rather than the vectorizer's fault: the loop
is vectorized basically into "mem = {0,0}" in TImode, which is later
expanded to the following RTL:

(insn:HI 21 19 22 1 (set (mem:TI (reg/f:SI 2 r2 [129]) [4 S16 A128])
        (reg:TI 5 r5 [130])) 316 {*movti_string} (insn_list:REG_DEP_TRUE 19
(nil)))

where reg 130 is set to 0 before the loop:

(insn:HI 80 15 104 0 (set (reg:TI 5 r5 [130])
        (const_int 0 [0x0])) 316 {*movti_string} (nil))


but after flow2 (looking at vect-82.c.26.flow2) this becomes:

(insn 106 19 107 1 (set (mem:SI (reg/f:SI 2 r2 [129]) [4 S4 A128])
        (reg:SI 5 r5)) 295 {*movsi_internal1} (nil))
(insn 107 106 108 1 (set (mem:SI (plus:SI (reg/f:SI 2 r2 [129])
                (const_int 4 [0x4])) [4 S4 A32])
        (reg:SI 6 r6 [+4 ])) 295 {*movsi_internal1} (nil))
(insn 108 107 109 1 (set (mem:SI (plus:SI (reg/f:SI 2 r2 [129])
                (const_int 8 [0x8])) [4 S4 A64])
        (reg:SI 7 r7 [+8 ])) 295 {*movsi_internal1} (nil))
(insn 109 108 22 1 (set (mem:SI (plus:SI (reg/f:SI 2 r2 [129])
                (const_int 12 [0xc])) [4 S4 A32])
        (reg:SI 8 r8 [orig:130+12 ] [130])) 295 {*movsi_internal1} (nil))


or, if I use -mpowerpc64, it becomes:

(insn 108 27 109 1 (set (mem:DI (reg/f:SI 2 r2 [134]) [4 S8 A128])
        (reg:DI 9 r9)) 314 {*movdi_internal64} (nil))
(insn 109 108 91 1 (set (mem:DI (plus:SI (reg/f:SI 2 r2 [134])
                (const_int 8 [0x8])) [4 S8 A64])
        (reg:DI 10 r10 [orig:135+8 ] [135])) 314 {*movdi_internal64} (nil))


In other words, the effect is that vectorization is undone and everything
is emulated with scalar operations. Were you expecting to see simd vectors
generated? If so, this might be related to PR18506 ?
dorit