MIPS patch to correct move zero type attributes

[James E Wilson]

Another item on my mips vector patch cleanup list.

The FP move patterns all have a m/fG alternative with type fpstore,
which is incorrect for m/G.  This patch make the obvious changes to fix
this, by splitting fG into two alternatives.

This was tested with an sb1-elf cross compiler from a combined tree
build, C and C++ only, and a make check.  There were no regressions. 
There were 36 fewer libstdc++ failures, but I suspect that is due to one
of my other bug fixes made since the last time I ran the sb1-elf
testsuite, perhaps my tree-ssa-alias.c patch.
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com

-------------- next part --------------
2004-09-03  James E Wilson  <wilson@specifixinc.com>

	* config/mips/mips.md (movsf_hardfloat, movdf_hardfloat_64bit,
	movdf_hardfloat_32bit): Split fG into two alternatives.
	(movv2sf_hardfloat_64bit): Split fYG into two alternatives.

Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.302
diff -p -p -r1.302 mips.md
*** mips.md	3 Sep 2004 20:12:28 -0000	1.302
--- mips.md	4 Sep 2004 02:09:57 -0000
*************** beq\t%2,%.,1b\;\
*** 3808,3822 ****
  })
  
  (define_insn "*movsf_hardfloat"
!   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
! 	(match_operand:SF 1 "move_operand" "f,G,m,fG,*d,*f,*G*d,*m,*d"))]
    "TARGET_HARD_FLOAT
     && (register_operand (operands[0], SFmode)
         || reg_or_0_operand (operands[1], SFmode))"
    { return mips_output_move (operands[0], operands[1]); }
!   [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
     (set_attr "mode"	"SF")
!    (set_attr "length"	"4,4,*,*,4,4,4,*,*")])
  
  (define_insn "*movsf_softfloat"
    [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
--- 3808,3822 ----
  })
  
  (define_insn "*movsf_hardfloat"
!   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
! 	(match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
    "TARGET_HARD_FLOAT
     && (register_operand (operands[0], SFmode)
         || reg_or_0_operand (operands[1], SFmode))"
    { return mips_output_move (operands[0], operands[1]); }
!   [(set_attr "type"	"fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
     (set_attr "mode"	"SF")
!    (set_attr "length"	"4,4,*,*,*,4,4,4,*,*")])
  
  (define_insn "*movsf_softfloat"
    [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
*************** beq\t%2,%.,1b\;\
*** 3853,3878 ****
  })
  
  (define_insn "*movdf_hardfloat_64bit"
!   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
! 	(match_operand:DF 1 "move_operand" "f,G,m,fG,*d,*f,*d*G,*m,*d"))]
    "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
     && (register_operand (operands[0], DFmode)
         || reg_or_0_operand (operands[1], DFmode))"
    { return mips_output_move (operands[0], operands[1]); }
!   [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
     (set_attr "mode"	"DF")
!    (set_attr "length"	"4,4,*,*,4,4,4,*,*")])
  
  (define_insn "*movdf_hardfloat_32bit"
!   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
! 	(match_operand:DF 1 "move_operand" "f,G,m,fG,*d,*f,*d*G,*m,*d"))]
    "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
     && (register_operand (operands[0], DFmode)
         || reg_or_0_operand (operands[1], DFmode))"
    { return mips_output_move (operands[0], operands[1]); }
!   [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
     (set_attr "mode"	"DF")
!    (set_attr "length"	"4,8,*,*,8,8,8,*,*")])
  
  (define_insn "*movdf_softfloat"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
--- 3853,3878 ----
  })
  
  (define_insn "*movdf_hardfloat_64bit"
!   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
! 	(match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
    "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
     && (register_operand (operands[0], DFmode)
         || reg_or_0_operand (operands[1], DFmode))"
    { return mips_output_move (operands[0], operands[1]); }
!   [(set_attr "type"	"fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
     (set_attr "mode"	"DF")
!    (set_attr "length"	"4,4,*,*,*,4,4,4,*,*")])
  
  (define_insn "*movdf_hardfloat_32bit"
!   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
! 	(match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
    "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
     && (register_operand (operands[0], DFmode)
         || reg_or_0_operand (operands[1], DFmode))"
    { return mips_output_move (operands[0], operands[1]); }
!   [(set_attr "type"	"fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
     (set_attr "mode"	"DF")
!    (set_attr "length"	"4,8,*,*,*,8,8,8,*,*")])
  
  (define_insn "*movdf_softfloat"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
*************** beq\t%2,%.,1b\;\
*** 3945,3960 ****
  })
  
  (define_insn "movv2sf_hardfloat_64bit"
!   [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
! 	(match_operand:V2SF 1 "move_operand" "f,YG,m,fYG,*d,*f,*d*YG,*m,*d"))]
    "TARGET_PAIRED_SINGLE_FLOAT
     && TARGET_64BIT
     && (register_operand (operands[0], V2SFmode)
         || reg_or_0_operand (operands[1], V2SFmode))"
    { return mips_output_move (operands[0], operands[1]); }
!   [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
     (set_attr "mode" "SF")
!    (set_attr "length" "4,4,*,*,4,4,4,*,*")])
  
  ;; The HI and LO registers are not truly independent.  If we move an mthi
  ;; instruction before an mflo instruction, it will make the result of the
--- 3945,3960 ----
  })
  
  (define_insn "movv2sf_hardfloat_64bit"
!   [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
! 	(match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
    "TARGET_PAIRED_SINGLE_FLOAT
     && TARGET_64BIT
     && (register_operand (operands[0], V2SFmode)
         || reg_or_0_operand (operands[1], V2SFmode))"
    { return mips_output_move (operands[0], operands[1]); }
!   [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
     (set_attr "mode" "SF")
!    (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
  
  ;; The HI and LO registers are not truly independent.  If we move an mthi
  ;; instruction before an mflo instruction, it will make the result of the