RFC: modify ppc expanders to support e500
Aldy Hernandez
aldyh@redhat.com
Sat Oct 23 00:39:00 GMT 2004
On Fri, Oct 22, 2004 at 05:33:16PM -0400, David Edelsohn wrote:
> The first thing that jumps out to me is a style comment.
> fpr_extendsfdf2 is not referenced anywhere else that I can see in the
> patch, so the name should be prepended with "*". Second, the rest of the
Woah. Did not know unreferenced patterns should be *prefaced. Fixed.
> port generally makes the name unique at the end, e.g., "*extendsfdf2_fpr"
> or "*extendsfdf2_noe500".
Fixed all patterns. See below.
See patch.
I'd like an ok from you guys before I commit this.
Thanks.
Aldy
* config/rs6000/rs6000.md (fix_truncdffsi2): Handle e500
doubles.
(floatunssidf2): Same.
(floatsidf2): Same.
* config/rs6000/spe.md ("spe_extendsfdf2"): Remove FIXME comment.
("spe_fix_truncdfsi2"): Same.
(spe_floatunssidf2): Same.
(spe_floatsidf2): Same.
* config/rs6000/rs6000.md ("extendsfdf2"): New expander.
(*extendsfdf2_fpr): Rename.
(*truncdfsf2_fpr): Same.
(*negdf2_fpr): Same.
(*absdf2_fpr): Same.
(*nabsdf2_fpr): Same.
(*adddf3_fpr): Same.
(*subdf3_fpr): Same.
(*muldf3_fpr): Same.
(*divdf3_fpr): Same.
Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.325
diff -c -p -r1.325 rs6000.md
*** config/rs6000/rs6000.md 22 Oct 2004 19:41:58 -0000 1.325
--- config/rs6000/rs6000.md 22 Oct 2004 23:13:08 -0000
***************
*** 4459,4465 ****
;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point.
! (define_insn_and_split "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
--- 4459,4471 ----
;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point.
! (define_expand "extendsfdf2"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn_and_split "*extendsfdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
***************
*** 4480,4486 ****
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "fpr_truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
--- 4486,4492 ----
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
***************
*** 4876,4882 ****
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "fpr_negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
--- 4882,4888 ----
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "*negdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
***************
*** 4889,4902 ****
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "fpr_absdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
[(set_attr "type" "fp")])
! (define_insn "fpr_nabsdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
--- 4895,4908 ----
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "*absdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
[(set_attr "type" "fp")])
! (define_insn "*nabsdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
***************
*** 4910,4916 ****
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "fpr_adddf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 4916,4922 ----
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "*adddf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
***************
*** 4925,4931 ****
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "fpr_subdf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 4931,4937 ----
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "*subdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
***************
*** 4940,4946 ****
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "fpr_muldf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 4946,4952 ----
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "*muldf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
***************
*** 4955,4961 ****
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "fpr_divdf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 4961,4967 ----
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
! (define_insn "*divdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
***************
*** 5126,5131 ****
--- 5132,5142 ----
"TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
+ DONE;
+ }
if (TARGET_POWERPC64)
{
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
***************
*** 5205,5213 ****
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
! "TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
if (TARGET_POWERPC64)
{
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
--- 5216,5229 ----
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
+ DONE;
+ }
if (TARGET_POWERPC64)
{
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
***************
*** 5274,5282 ****
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
(clobber (match_dup 2))
(clobber (match_dup 3))])]
! "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
operands[2] = gen_reg_rtx (DImode);
operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
}")
--- 5290,5303 ----
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
(clobber (match_dup 2))
(clobber (match_dup 3))])]
! "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
+ DONE;
+ }
operands[2] = gen_reg_rtx (DImode);
operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
}")
Index: config/rs6000/spe.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/spe.md,v
retrieving revision 1.28
diff -c -p -r1.28 spe.md
*** config/rs6000/spe.md 22 Oct 2004 19:41:58 -0000 1.28
--- config/rs6000/spe.md 22 Oct 2004 23:13:08 -0000
***************
*** 93,99 ****
"efdctuiz %0,%1"
[(set_attr "type" "fp")])
- ;; FIXME: fix expander.
(define_insn "spe_extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
--- 93,98 ----
***************
*** 115,121 ****
"efsctsiz %0,%1"
[(set_attr "type" "fp")])
- ;; FIXME: fix expander.
(define_insn "spe_fix_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
--- 114,119 ----
***************
*** 130,136 ****
"efscfui %0,%1"
[(set_attr "type" "fp")])
- ;; FIXME: fix expander.
(define_insn "spe_floatunssidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
--- 128,133 ----
***************
*** 145,151 ****
"efscfsi %0,%1"
[(set_attr "type" "fp")])
- ;; FIXME: fix expander.
(define_insn "spe_floatsidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
--- 142,147 ----
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