S/390: Annotate S-type memory operands with format flag
Ulrich Weigand
weigand@i1.informatik.uni-erlangen.de
Mon Oct 11 21:01:00 GMT 2004
Hello,
this adds an 'S' format flag to be used for S-type memory operands (i.e. those
without index register). This is currently just an additional check to ensure
we have the correct constraints; it also allows operand output routines to
choose different formats for S and X memory operands.
In going through the md file and marking up the insns, I noticed a couple of
(irrelevant) mistakes, which are fixed here as well.
Bootstrapped/regtested on s390-ibm-linux and s390x-ibm-linux,
committed to mainline.
Bye,
Ulrich
ChangeLog:
* config/s390/s390.c (print_operand): Support 'S' format flag.
* config/s390/s390.md ("*tmqi_mem"): Use 'S' format flag.
("*tstsi", "*tstsi_cconly", "*tstsi_cconly2"): Likewise.
("*tsthiCCT", "*tsthiCCT_cconly", "*tsthi", "*tsthi_cconly"): Likewise.
("*tstqiCCT", "*tstqiCCT_cconly", "*tstqi", "*tstqi_cconly"): Likewise.
("*cmphi_ccu", "*cmpqi_ccu", "*clc"): Likewise
("movti", "*movdi_31", "*movqi", "*movdf_31", "*mvc"): Likewise.
("*movstricthi"): Likewise.
("*load_multiple_di", "*load_multiple_si"): Likewise.
("*store_multiple_di", "*store_multiple_si"): Likewise.
("*sethiqisi", "*sethihisi"): Likewise.
("*sethiqidi_64", "*sethiqidi_31"): Likewise.
("*andqi3_zarch", "*andqi3_esa", "*nc"): Likewise.
("*iorqi3_zarch", "*iorqi3_esa", "*oc"): Likewise.
("*xorqi3", "*xc", "*xc_zero"): Likewise.
("get_tp_64", "get_tp_31", "set_tp_64", "set_tp_31"): Likewise.
("*tmhi_full"): Fix incorrect op_type attribute.
("*adddi3_alc_cc", "*adddi3_alc"): Remove double backslash.
("*subdi3_slb_cc", "*subdi3_slb"): Likewise.
("*addsi3_alc_cc", "*addsi3_alc"): Likewise.
("*subsi3_slb_cc", "*subsi3_slb"): Likewise.
Index: gcc/config/s390/s390.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.c,v
retrieving revision 1.191
diff -c -p -r1.191 s390.c
*** gcc/config/s390/s390.c 11 Oct 2004 18:28:23 -0000 1.191
--- gcc/config/s390/s390.c 11 Oct 2004 18:57:38 -0000
*************** print_operand_address (FILE *file, rtx a
*** 4066,4071 ****
--- 4066,4072 ----
'J': print tls_load/tls_gdcall/tls_ldcall suffix
'O': print only the displacement of a memory reference.
'R': print only the base register of a memory reference.
+ 'S': print S-type memory reference (base+displacement).
'N': print the second word of a DImode operand.
'M': print the second word of a TImode operand.
'Y': print shift count operand.
*************** print_operand (FILE *file, rtx x, int co
*** 4143,4148 ****
--- 4144,4169 ----
}
return;
+ case 'S':
+ {
+ struct s390_address ad;
+
+ if (GET_CODE (x) != MEM
+ || !s390_decompose_address (XEXP (x, 0), &ad)
+ || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
+ || ad.indx)
+ abort ();
+
+ if (ad.disp)
+ output_addr_const (file, ad.disp);
+ else
+ fprintf (file, "0");
+
+ if (ad.base)
+ fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
+ }
+ return;
+
case 'N':
if (GET_CODE (x) == REG)
x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.134
diff -c -p -r1.134 s390.md
*** gcc/config/s390/s390.md 11 Oct 2004 14:33:25 -0000 1.134
--- gcc/config/s390/s390.md 11 Oct 2004 18:57:39 -0000
***************
*** 60,65 ****
--- 60,66 ----
;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
;; %O: print only the displacement of a memory reference.
;; %R: print only the base register of a memory reference.
+ ;; %S: print S-type memory reference (base+displacement).
;; %N: print the second word of a DImode operand.
;; %M: print the second word of a TImode operand.
***************
*** 302,309 ****
(match_operand:QI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
"@
! tm\t%0,%b1
! tmy\t%0,%b1"
[(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg"
--- 303,310 ----
(match_operand:QI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
"@
! tm\t%S0,%b1
! tmy\t%S0,%b1"
[(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg"
***************
*** 340,346 ****
(match_operand:HI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
"tml\t%0,65535"
! [(set_attr "op_type" "RX")])
(define_insn "*tmqi_full"
[(set (reg 33)
--- 341,347 ----
(match_operand:HI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
"tml\t%0,65535"
! [(set_attr "op_type" "RI")])
(define_insn "*tmqi_full"
[(set (reg 33)
***************
*** 401,408 ****
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\t%2,%0
! icm\t%2,15,%0
! icmy\t%2,15,%0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly"
--- 402,409 ----
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\t%2,%0
! icm\t%2,15,%S0
! icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly"
***************
*** 413,420 ****
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\t%0,%0
! icm\t%2,15,%0
! icmy\t%2,15,%0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2"
--- 414,421 ----
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\t%0,%0
! icm\t%2,15,%S0
! icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2"
***************
*** 433,440 ****
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
! icm\t%2,3,%0
! icmy\t%2,3,%0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")])
--- 434,441 ----
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
! icm\t%2,3,%S0
! icmy\t%2,3,%S0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")])
***************
*** 445,452 ****
(clobber (match_scratch:HI 2 "=d,d,X"))]
"s390_match_ccmode(insn, CCTmode)"
"@
! icm\t%2,3,%0
! icmy\t%2,3,%0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")])
--- 446,453 ----
(clobber (match_scratch:HI 2 "=d,d,X"))]
"s390_match_ccmode(insn, CCTmode)"
"@
! icm\t%2,3,%S0
! icmy\t%2,3,%S0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")])
***************
*** 458,465 ****
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
! icm\t%2,3,%0
! icmy\t%2,3,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tsthi_cconly"
--- 459,466 ----
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
! icm\t%2,3,%S0
! icmy\t%2,3,%S0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tsthi_cconly"
***************
*** 469,476 ****
(clobber (match_scratch:HI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
! icm\t%2,3,%0
! icmy\t%2,3,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqiCCT"
--- 470,477 ----
(clobber (match_scratch:HI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
! icm\t%2,3,%S0
! icmy\t%2,3,%S0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqiCCT"
***************
*** 481,488 ****
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
! icm\t%2,1,%0
! icmy\t%2,1,%0
tml\t%0,255"
[(set_attr "op_type" "RS,RSY,RI")])
--- 482,489 ----
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
! icm\t%2,1,%S0
! icmy\t%2,1,%S0
tml\t%0,255"
[(set_attr "op_type" "RS,RSY,RI")])
***************
*** 492,499 ****
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
"@
! cli\t%0,0
! cliy\t%0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")])
--- 493,500 ----
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
"@
! cli\t%S0,0
! cliy\t%S0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")])
***************
*** 505,512 ****
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
! icm\t%2,1,%0
! icmy\t%2,1,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqi_cconly"
--- 506,513 ----
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
! icm\t%2,1,%S0
! icmy\t%2,1,%S0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqi_cconly"
***************
*** 516,523 ****
(clobber (match_scratch:QI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
! icm\t%2,1,%0
! icmy\t%2,1,%0"
[(set_attr "op_type" "RS,RSY")])
--- 517,524 ----
(clobber (match_scratch:QI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
! icm\t%2,1,%S0
! icmy\t%2,1,%S0"
[(set_attr "op_type" "RS,RSY")])
***************
*** 645,652 ****
&& (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))
&& !register_operand (operands[1], HImode)"
"@
! clm\t%0,3,%1
! clmy\t%0,3,%1
#"
[(set_attr "op_type" "RS,RSY,SS")])
--- 646,653 ----
&& (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))
&& !register_operand (operands[1], HImode)"
"@
! clm\t%0,3,%S1
! clmy\t%0,3,%S1
#"
[(set_attr "op_type" "RS,RSY,SS")])
***************
*** 658,667 ****
&& (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))
&& !register_operand (operands[1], QImode)"
"@
! clm\t%0,1,%1
! clmy\t%0,1,%1
! cli\t%0,%b1
! cliy\t%0,%b1
#"
[(set_attr "op_type" "RS,RSY,SI,SIY,SS")])
--- 659,668 ----
&& (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))
&& !register_operand (operands[1], QImode)"
"@
! clm\t%0,1,%S1
! clmy\t%0,1,%S1
! cli\t%S0,%b1
! cliy\t%S0,%b1
#"
[(set_attr "op_type" "RS,RSY,SI,SIY,SS")])
***************
*** 675,681 ****
(use (match_operand 2 "const_int_operand" "n"))]
"s390_match_ccmode (insn, CCUmode)
&& INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "clc\t%O0(%2,%R0),%1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
--- 676,682 ----
(use (match_operand 2 "const_int_operand" "n"))]
"s390_match_ccmode (insn, CCUmode)
&& INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "clc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
***************
*** 800,807 ****
(match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
"TARGET_64BIT"
"@
! lmg\t%0,%N0,%1
! stmg\t%1,%N1,%0
#
#
#"
--- 801,808 ----
(match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
"TARGET_64BIT"
"@
! lmg\t%0,%N0,%S1
! stmg\t%1,%N1,%S0
#
#
#"
***************
*** 914,921 ****
(match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT"
"@
! lm\t%0,%N0,%1
! stm\t%1,%N1,%0
#
#
ldr\t%0,%1
--- 915,922 ----
(match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT"
"@
! lm\t%0,%N0,%S1
! stm\t%1,%N1,%S0
#
#
ldr\t%0,%1
***************
*** 1271,1278 ****
icy\t%0,%1
stc\t%1,%0
stcy\t%1,%0
! mvi\t%0,%b1
! mviy\t%0,%b1
#"
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
(set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
--- 1272,1279 ----
icy\t%0,%1
stc\t%1,%0
stcy\t%1,%0
! mvi\t%S0,%b1
! mviy\t%S0,%b1
#"
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
(set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
***************
*** 1310,1317 ****
(clobber (reg:CC 33))]
""
"@
! icm\t%0,3,%1
! icmy\t%0,3,%1"
[(set_attr "op_type" "RS,RSY")])
;
--- 1311,1318 ----
(clobber (reg:CC 33))]
""
"@
! icm\t%0,3,%S1
! icmy\t%0,3,%S1"
[(set_attr "op_type" "RS,RSY")])
;
***************
*** 1366,1373 ****
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
! lm\t%0,%N0,%1
! stm\t%1,%N1,%0
#
#
#"
--- 1367,1374 ----
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
! lm\t%0,%N0,%S1
! stm\t%1,%N1,%S0
#
#
#"
***************
*** 1459,1465 ****
(match_operand:BLK 1 "memory_operand" "Q"))
(use (match_operand 2 "const_int_operand" "n"))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "mvc\t%O0(%2,%R0),%1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
--- 1460,1466 ----
(match_operand:BLK 1 "memory_operand" "Q"))
(use (match_operand 2 "const_int_operand" "n"))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "mvc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
***************
*** 1572,1578 ****
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
! return "lmg\t%1,%0,%2";
}
[(set_attr "op_type" "RSY")
(set_attr "type" "lm")])
--- 1573,1579 ----
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
! return "lmg\t%1,%0,%S2";
}
[(set_attr "op_type" "RSY")
(set_attr "type" "lm")])
***************
*** 1585,1591 ****
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
! return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2";
}
[(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")])
--- 1586,1592 ----
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
! return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
}
[(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")])
***************
*** 1663,1669 ****
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
! return "stmg\t%2,%0,%1";
}
[(set_attr "op_type" "RSY")
(set_attr "type" "stm")])
--- 1664,1670 ----
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
! return "stmg\t%2,%0,%S1";
}
[(set_attr "op_type" "RSY")
(set_attr "type" "stm")])
***************
*** 1677,1683 ****
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
! return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1";
}
[(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")])
--- 1678,1684 ----
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
! return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
}
[(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")])
***************
*** 2262,2269 ****
(clobber (reg:CC 33))]
""
"@
! icm\t%0,8,%1
! icmy\t%0,8,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighhisi"
--- 2263,2270 ----
(clobber (reg:CC 33))]
""
"@
! icm\t%0,8,%S1
! icmy\t%0,8,%S1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighhisi"
***************
*** 2272,2279 ****
(clobber (reg:CC 33))]
""
"@
! icm\t%0,12,%1
! icmy\t%0,12,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighqidi_64"
--- 2273,2280 ----
(clobber (reg:CC 33))]
""
"@
! icm\t%0,12,%S1
! icmy\t%0,12,%S1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighqidi_64"
***************
*** 2281,2287 ****
(unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
(clobber (reg:CC 33))]
"TARGET_64BIT"
! "icmh\t%0,8,%1"
[(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31"
--- 2282,2288 ----
(unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
(clobber (reg:CC 33))]
"TARGET_64BIT"
! "icmh\t%0,8,%S1"
[(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31"
***************
*** 2290,2297 ****
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"@
! icm\t%0,8,%1
! icmy\t%0,8,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn_and_split "*extractqi"
--- 2291,2298 ----
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"@
! icm\t%0,8,%S1
! icmy\t%0,8,%S1"
[(set_attr "op_type" "RS,RSY")])
(define_insn_and_split "*extractqi"
***************
*** 4230,4237 ****
(plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
! alcgr\\t%0,%2
! alcg\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_alc"
--- 4231,4238 ----
(plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
! alcgr\t%0,%2
! alcg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_alc"
***************
*** 4242,4249 ****
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
! alcgr\\t%0,%2
! alcg\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_slb_cc"
--- 4243,4250 ----
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
! alcgr\t%0,%2
! alcg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_slb_cc"
***************
*** 4257,4264 ****
(minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
! slbgr\\t%0,%2
! slbg\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_slb"
--- 4258,4265 ----
(minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
! slbgr\t%0,%2
! slbg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_slb"
***************
*** 4269,4276 ****
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
! slbgr\\t%0,%2
! slbg\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_expand "adddicc"
--- 4270,4277 ----
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
! slbgr\t%0,%2
! slbg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_expand "adddicc"
***************
*** 4299,4306 ****
(plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
! alcr\\t%0,%2
! alc\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*addsi3_alc"
--- 4300,4307 ----
(plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
! alcr\t%0,%2
! alc\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*addsi3_alc"
***************
*** 4311,4318 ****
(clobber (reg:CC 33))]
"TARGET_CPU_ZARCH"
"@
! alcr\\t%0,%2
! alc\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subsi3_slb_cc"
--- 4312,4319 ----
(clobber (reg:CC 33))]
"TARGET_CPU_ZARCH"
"@
! alcr\t%0,%2
! alc\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subsi3_slb_cc"
***************
*** 4326,4333 ****
(minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
! slbr\\t%0,%2
! slb\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subsi3_slb"
--- 4327,4334 ----
(minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
! slbr\t%0,%2
! slb\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subsi3_slb"
***************
*** 4338,4345 ****
(clobber (reg:CC 33))]
"TARGET_CPU_ZARCH"
"@
! slbr\\t%0,%2
! slb\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_expand "addsicc"
--- 4339,4346 ----
(clobber (reg:CC 33))]
"TARGET_CPU_ZARCH"
"@
! slbr\t%0,%2
! slb\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_expand "addsicc"
***************
*** 5374,5381 ****
"@
nr\t%0,%2
nill\t%0,%b2
! ni\t%0,%b2
! niy\t%0,%b2
#"
[(set_attr "op_type" "RR,RI,SI,SIY,SS")])
--- 5375,5382 ----
"@
nr\t%0,%2
nill\t%0,%b2
! ni\t%S0,%b2
! niy\t%S0,%b2
#"
[(set_attr "op_type" "RR,RI,SI,SIY,SS")])
***************
*** 5387,5393 ****
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
! ni\t%0,%b2
#"
[(set_attr "op_type" "RR,SI,SS")])
--- 5388,5394 ----
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
! ni\t%S0,%b2
#"
[(set_attr "op_type" "RR,SI,SS")])
***************
*** 5410,5416 ****
(use (match_operand 2 "const_int_operand" "n"))
(clobber (reg:CC 33))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "nc\t%O0(%2,%R0),%1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
--- 5411,5417 ----
(use (match_operand 2 "const_int_operand" "n"))
(clobber (reg:CC 33))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "nc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
***************
*** 5664,5671 ****
"@
or\t%0,%2
oill\t%0,%b2
! oi\t%0,%b2
! oiy\t%0,%b2
#"
[(set_attr "op_type" "RR,RI,SI,SIY,SS")])
--- 5665,5672 ----
"@
or\t%0,%2
oill\t%0,%b2
! oi\t%S0,%b2
! oiy\t%S0,%b2
#"
[(set_attr "op_type" "RR,RI,SI,SIY,SS")])
***************
*** 5677,5683 ****
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
! oi\t%0,%b2
#"
[(set_attr "op_type" "RR,SI,SS")])
--- 5678,5684 ----
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
! oi\t%S0,%b2
#"
[(set_attr "op_type" "RR,SI,SS")])
***************
*** 5700,5706 ****
(use (match_operand 2 "const_int_operand" "n"))
(clobber (reg:CC 33))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "oc\t%O0(%2,%R0),%1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
--- 5701,5707 ----
(use (match_operand 2 "const_int_operand" "n"))
(clobber (reg:CC 33))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "oc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
***************
*** 5920,5927 ****
"s390_logical_operator_ok_p (operands)"
"@
xr\t%0,%2
! xi\t%0,%b2
! xiy\t%0,%b2
#"
[(set_attr "op_type" "RR,SI,SIY,SS")])
--- 5921,5928 ----
"s390_logical_operator_ok_p (operands)"
"@
xr\t%0,%2
! xi\t%S0,%b2
! xiy\t%S0,%b2
#"
[(set_attr "op_type" "RR,SI,SIY,SS")])
***************
*** 5944,5950 ****
(use (match_operand 2 "const_int_operand" "n"))
(clobber (reg:CC 33))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "xc\t%O0(%2,%R0),%1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
--- 5945,5951 ----
(use (match_operand 2 "const_int_operand" "n"))
(clobber (reg:CC 33))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
! "xc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
***************
*** 6000,6006 ****
(use (match_operand 1 "const_int_operand" "n"))
(clobber (reg:CC 33))]
"INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
! "xc\t%O0(%1,%R0),%0"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
--- 6001,6007 ----
(use (match_operand 1 "const_int_operand" "n"))
(clobber (reg:CC 33))]
"INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
! "xc\t%O0(%1,%R0),%S0"
[(set_attr "op_type" "SS")
(set_attr "type" "cs")])
***************
*** 7423,7429 ****
"TARGET_64BIT"
"@
ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1
! stam\t%%a0,%%a1,%0"
[(set_attr "op_type" "NN,RS")
(set_attr "atype" "reg,*")
(set_attr "type" "o3,*")
--- 7424,7430 ----
"TARGET_64BIT"
"@
ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1
! stam\t%%a0,%%a1,%S0"
[(set_attr "op_type" "NN,RS")
(set_attr "atype" "reg,*")
(set_attr "type" "o3,*")
***************
*** 7435,7441 ****
"!TARGET_64BIT"
"@
ear\t%0,%%a0
! stam\t%%a0,%%a0,%0"
[(set_attr "op_type" "RRE,RS")])
(define_insn "set_tp_64"
--- 7436,7442 ----
"!TARGET_64BIT"
"@
ear\t%0,%%a0
! stam\t%%a0,%%a0,%S0"
[(set_attr "op_type" "RRE,RS")])
(define_insn "set_tp_64"
***************
*** 7444,7450 ****
"TARGET_64BIT"
"@
sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1
! lam\t%%a0,%%a1,%0"
[(set_attr "op_type" "NN,RS")
(set_attr "atype" "reg,*")
(set_attr "type" "o3,*")
--- 7445,7451 ----
"TARGET_64BIT"
"@
sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1
! lam\t%%a0,%%a1,%S0"
[(set_attr "op_type" "NN,RS")
(set_attr "atype" "reg,*")
(set_attr "type" "o3,*")
***************
*** 7455,7461 ****
"!TARGET_64BIT"
"@
sar\t%%a0,%0
! lam\t%%a0,%%a0,%0"
[(set_attr "op_type" "RRE,RS")])
(define_insn "*tls_load_64"
--- 7456,7462 ----
"!TARGET_64BIT"
"@
sar\t%%a0,%0
! lam\t%%a0,%%a0,%S0"
[(set_attr "op_type" "RRE,RS")])
(define_insn "*tls_load_64"
--
Dr. Ulrich Weigand
weigand@informatik.uni-erlangen.de
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