[RFC] PowerPC scheduling multi-instruction patterns

[David Edelsohn]

>>>>> Richard Henderson writes:

Richard> If the pattern will not execute in parallel, and the final instruction
Richard> in the pattern is issued two cycles after the first instruction in the
Richard> pattern, and the final instruction in the pattern has latency 1, then
Richard> it follows that the pattern as a whole has latency 3.

	I have performed some additional experiments using SPEC and the
default latency value does not have any effect on the overall performance
result.

	Looking at specific multi-instruction code sequences that exercise
the new scheduler descriptions, the GCC scheduler's internal concept of
processor cycle ticks does not schedule instructions until function unit
resources are available.  The larger default latency increases the
instruction's priority -- the multi-instruction sequences are emitted
earlier.  However, the scheduler does not overbook the function units and
does not assume that it can schedule other instructions in parallel with
low-latency multi-instruction sequence because the function units are
occupied in the automata.

	Because the sequence of simple, integer ops have internal data
dependencies, not a single instruction occuping a function unit for a long
time, if the processor cannot cover the latency with out-of-order issue,
the delay is going to hit eventually.

	Let me know if there is anything else that you think we should be
considering. 

Thanks, David