PATCH - FSF mainline canonicalization of AltyVec altivec_vandc pattern

[Fariborz Jahanian]

Following AltiVec test case compiled with -O1 and above produces 
inefficient code.

vector unsigned int
vand ( vector unsigned int A, vector unsigned int B)
{
         return vec_andc (A, B);
}

_vand:
         vnor  v3,v3,v3
         vand v2,v2,v3

Instead of:

_vand:
         vandc v2,v2,v3

This is because pattern altivec_vandc is not in its canonical form. 
This results in the combine
phase not to find the matching canonicalized pattern. It then proceeds 
to split the RTL into an
'and' of a 'not'.

Following patch, bootstrapped and dejagnu tested on apple-ppc-darwin 
fixes it.

OK for FSF mainline?

- Fariborz (fjahanian@apple.com).


ChangeLog:

2004-11-16  Fariborz Jahanian <fjahanian@apple.com>

         * config/rs6000/altivec.md (altivec_vandc): Canonicalize
         the pattern.


Index: altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.1.2.11.2.8
diff -c -p -r1.1.2.11.2.8 altivec.md
*** altivec.md  11 Nov 2004 01:13:56 -0000      1.1.2.11.2.8
--- altivec.md  16 Nov 2004 16:08:04 -0000
***************
*** 463,472 ****

   (define_insn "altivec_vandc"
     [(set (match_operand:V4SI 0 "register_operand" "=v")
!         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
!                   (not:V4SI (match_operand:V4SI 2 "register_operand" 
"v"))))]
     "TARGET_ALTIVEC"
!   "vandc %0,%1,%2"
     [(set_attr "type" "vecsimple")])

   (define_insn "altivec_vavgub"
--- 463,472 ----

   (define_insn "altivec_vandc"
     [(set (match_operand:V4SI 0 "register_operand" "=v")
!         (and:V4SI (not:V4SI (match_operand:V4SI 1 "register_operand" 
"v"))
!                   (match_operand:V4SI 2 "register_operand" "v")))]
     "TARGET_ALTIVEC"
!   "vandc %0,%2,%1"
     [(set_attr "type" "vecsimple")])

   (define_insn "altivec_vavgub"