[committed] Generalise mips16 li/neg splitter

[Richard Sandiford]

This patch generalises the SImode mips16 li/neg splitter so that
it can cope with other modes too.  It also alters the output templates
to force a split (via "#") rather than using "li ...\;neg ...".

Tested by compiling c-torture at -O2 -mips16 before and after the patch.
As expected, the only changes were that some "neg"s can now be scheduled
separately, and sometimes be put into a delay slot.

Bootstrapped & regression tested on mips64{,el}-linux-gnu.  Applied to trunk.

Richard


	* config/mips/mips.c (mips_output_move): When generating mips16 code,
	force loads of negative constants to be split.
	* config/mips/mips.md (*movhi_mips16, *movqi_mips16): Likewise.
	Generalize SImode li/neg splitter to cope with other modes.

Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.429
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.429 mips.c
--- config/mips/mips.c	13 Jul 2004 07:44:59 -0000	1.429
+++ config/mips/mips.c	13 Jul 2004 19:17:26 -0000
@@ -2608,7 +2608,7 @@ mips_output_move (rtx dest, rtx src)
 	    return "li\t%0,%1";
 
 	  if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
-	    return "li\t%0,%n1\n\tneg\t%0";
+	    return "#";
 	}
 
       if (src_code == HIGH)
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.251
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.251 mips.md
--- config/mips/mips.md	12 Jul 2004 05:21:29 -0000	1.251
+++ config/mips/mips.md	13 Jul 2004 19:17:33 -0000
@@ -4289,22 +4289,6 @@ (define_split
   operands[2] = GEN_INT (val - 0xff);
 })
 
-;; On the mips16, we can split a load of a negative constant into a
-;; load and a neg.  That's what mips_output_move will generate anyhow.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand")
-	(match_operand:SI 1 "const_int_operand"))]
-  "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && INTVAL (operands[1]) < 0
-   && INTVAL (operands[1]) > - 0x8000"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (neg:SI (match_dup 0)))]
-  { operands[1] = GEN_INT (- INTVAL (operands[1])); })
-
 ;; This insn handles moving CCmode values.  It's really just a
 ;; slightly simplified copy of movsi_internal2, with additional cases
 ;; to move a condition register to a general register and to move
@@ -4492,7 +4476,7 @@ (define_insn "*movhi_mips16"
     move\t%0,%1
     move\t%0,%1
     li\t%0,%1
-    li\t%0,%n1\;neg\t%0
+    #
     lhu\t%0,%1
     sh\t%1,%0"
   [(set_attr "type"	"arith,arith,arith,arith,arith,load,store")
@@ -4599,7 +4583,7 @@ (define_insn "*movqi_mips16"
     move\t%0,%1
     move\t%0,%1
     li\t%0,%1
-    li\t%0,%n1\;neg\t%0
+    #
     lbu\t%0,%1
     sb\t%1,%0"
   [(set_attr "type"	"arith,arith,arith,arith,arith,load,store")
@@ -4758,6 +4742,21 @@ (define_split
   DONE;
 })
 
+;; When generating mips16 code, split moves of negative constants into
+;; a positive "li" followed by a negation.
+(define_split
+  [(set (match_operand 0 "register_operand")
+	(match_operand 1 "const_int_operand"))]
+  "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
+  [(set (match_dup 0)
+	(match_dup 2))
+   (set (match_dup 3)
+	(neg:SI (match_dup 3)))]
+{
+  operands[2] = GEN_INT (-INTVAL (operands[1]));
+  operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
 ;; The HI and LO registers are not truly independent.  If we move an mthi
 ;; instruction before an mflo instruction, it will make the result of the
 ;; mflo unpredictable.  The same goes for mtlo and mfhi.