[PATCH] Add floating point timings to rs6000_rtx_costs

[David Edelsohn]

>>>>> Roger Sayle writes:

Roger> The values that GCC's middle-end cares about are the latencies.
Roger> In almost all cases (RTL expansion, if-conversion, RTL simplification,
Roger> combine, etc...) the assumption is that rtx_cost is the "cost" or
Roger> "time" for the result to become available for use by the next
Roger> instruction, relative to a fast integer instruction.

Roger> I'm not sure if you've misread my patch, but all of the values in the
Roger> struct processor_cost table are scaled by COSTS_N_INSNS converting
Roger> them from pure hardware cycles, to "relative cycles" (additions).

	Yes, the cost is in *relative* cycles, which means that part of
your patch needs to be revised.  Thanks for clarifying that the cost is
unified for all instructions, not integer distinguished from floating
point.

	On POWER4/POWER5, the latency of fast, simple instructions is 2
cycles.  The cost of those instructions is COSTS_N_INSNS(1).  Your earlier
patch did not change that and there is no intention of enumerating the
cost of each trivial operation as COSTS_N_INSN(2) for those processors.

	The POWER4/POWER5 cost of multiplies in the original code and
carried over to your table already has been scaled for the integer latency
of 2, but the cost of FP operations in your patch has not been scaled.
You need to divide all of your FP costs for POWER4/POWER5 by 2.

Thanks, David