DFA "pipeline" description for mcore

[Jeffrey A Law]

On Sat, 2004-07-03 at 09:27, Steven Bosscher wrote:
> Hi,
> 
> There's really no "pipeline model" here, only a load latency of
> 2 cycles instead of 1 is modelled.  But in the DFA model, an insn
> that doesn't match a define_insn_reservation has latency 0, hence
> the extra lines.
> 
> Tested by building an amd64 x mcore cross and comparing assembly.
> OK?
> 
> Gr.
> Steven
> 
> 	* config/mcore/mcore.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE):
> 	Define.
> 	* config/mcore/mcore.md: Model memory latency with a simple DFA
> 	pipeline description instead of a define_function_unit.
This is fine.

jeff