DFA "pipeline" description for mcore

[Steven Bosscher]

Hi,

There's really no "pipeline model" here, only a load latency of
2 cycles instead of 1 is modelled.  But in the DFA model, an insn
that doesn't match a define_insn_reservation has latency 0, hence
the extra lines.

Tested by building an amd64 x mcore cross and comparing assembly.
OK?

Gr.
Steven

	* config/mcore/mcore.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE):
	Define.
	* config/mcore/mcore.md: Model memory latency with a simple DFA
	pipeline description instead of a define_function_unit.

Index: config/mcore/mcore.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mcore/mcore.c,v
retrieving revision 1.63
diff -c -3 -p -r1.63 mcore.c
*** config/mcore/mcore.c	8 Feb 2004 23:08:42 -0000	1.63
--- config/mcore/mcore.c	16 Jun 2004 22:07:44 -0000
*************** static bool       mcore_return_in_memory
*** 196,201 ****
--- 196,204 ----
  #undef  TARGET_SETUP_INCOMING_VARARGS
  #define TARGET_SETUP_INCOMING_VARARGS	mcore_setup_incoming_varargs
  
+ #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+ #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
+ 
  struct gcc_target targetm = TARGET_INITIALIZER;
  
  /* Adjust the stack and return the number of bytes taken to do it.  */
Index: config/mcore/mcore.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mcore/mcore.md,v
retrieving revision 1.16
diff -c -3 -p -r1.16 mcore.md
*** config/mcore/mcore.md	1 Feb 2004 21:21:40 -0000	1.16
--- config/mcore/mcore.md	16 Jun 2004 22:07:44 -0000
***************
*** 41,55 ****
  ;; calculations and the literal table placement into the assembler,
  ;; where their interactions can be managed in a single place.
  
! ; All MCORE instructions are two bytes long.
  
  (define_attr "length" "" (const_int 2))
  
! ;; (define_function_unit {name} {num-units} {n-users} {test}
! ;;                       {ready-delay} {issue-delay} [{conflict-list}])
! 				      
! 
! (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
  
  ;; -------------------------------------------------------------------------
  ;; Test and bit test
--- 41,57 ----
  ;; calculations and the literal table placement into the assembler,
  ;; where their interactions can be managed in a single place.
  
! ;; All MCORE instructions are two bytes long.
  
  (define_attr "length" "" (const_int 2))
  
! ;; Scheduling.  We only model a simple load latency.
! (define_insn_reservation "any_insn" 1
! 			 (eq_attr "type" "!load")
! 			 "nothing")
! (define_insn_reservation "memory" 2
! 			 (eq_attr "type" "load")
! 			 "nothing")
  
  ;; -------------------------------------------------------------------------
  ;; Test and bit test