[csl-arm]: tidy up variable names
Richard Earnshaw
rearnsha@arm.com
Thu Jan 8 11:10:00 GMT 2004
This patch is mainly a cleanup of some variable names in an attempt to
make the code slightly more self-documenting.
It renames
FL_FAST_MULT -> FL_ARCH3M
FL_ARCH6J -> FL_ARCH6
arm_fast_multiply -> arm_arch3m
arm_arch6j -> arm_arch6
The arch6 changes are done because the extra instructions enabled by this
flag are part of the base architecture v6 (not the v6J extension).
There's one technical fix: The preprocessor define for __ARM_ARCH_6J__
was being triggered by a cpu name not an architecture name (missing 'v').
I've also added an entry for __ARM_ARCH_6__.
Tested on an arm-elf cross.
R.
2004-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT.
(FL_ARCH6): Renamed from FL_ARCH6J.
(arm_arch3m): Renamed from arm_fast_multiply.
(arm_arch6): Renamed from arm_arch6j.
* arm.h: Update all uses of above.
* arm-cores.def: Likewise.
* arm.md: Likewise.
* arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j,
not arm6j. Add entry for arch armv6.
-------------- next part --------------
Index: arm-cores.def
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/Attic/arm-cores.def,v
retrieving revision 1.1.2.2
diff -p -r1.1.2.2 arm-cores.def
*** arm-cores.def 29 Dec 2003 18:24:10 -0000 1.1.2.2
--- arm-cores.def 8 Jan 2004 10:52:28 -0000
*************** ARM_CORE(arm620, FL_CO_PROC | FL_MODE26
*** 41,51 ****
ARM_CORE(arm7, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
/* arm7m doesn't exist on its own, but only with D, (and I), but
those don't alter the code, so arm7m is sometimes used. */
! ARM_CORE(arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT, fastmul)
ARM_CORE(arm7d, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
! ARM_CORE(arm7dm, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT, fastmul)
ARM_CORE(arm7di, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
! ARM_CORE(arm7dmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT, fastmul)
ARM_CORE(arm70, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
ARM_CORE(arm700, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
ARM_CORE(arm700i, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
--- 41,51 ----
ARM_CORE(arm7, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
/* arm7m doesn't exist on its own, but only with D, (and I), but
those don't alter the code, so arm7m is sometimes used. */
! ARM_CORE(arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M, fastmul)
ARM_CORE(arm7d, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
! ARM_CORE(arm7dm, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M, fastmul)
ARM_CORE(arm7di, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
! ARM_CORE(arm7dmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M, fastmul)
ARM_CORE(arm70, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
ARM_CORE(arm700, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
ARM_CORE(arm700i, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
*************** ARM_CORE(arm7500, FL_MODE26
*** 57,87 ****
/* Doesn't have an external co-proc, but does have embedded fpa. */
ARM_CORE(arm7500fe, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
/* V4 Architecture Processors */
! ARM_CORE(arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB, fastmul)
! ARM_CORE(arm710t, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB, fastmul)
! ARM_CORE(arm720t, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB, fastmul)
! ARM_CORE(arm740t, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB, fastmul)
! ARM_CORE(arm8, FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED, fastmul)
! ARM_CORE(arm810, FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED, fastmul)
! ARM_CORE(arm9, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul)
! ARM_CORE(arm920, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED, fastmul)
! ARM_CORE(arm920t, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul)
! ARM_CORE(arm940t, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul)
! ARM_CORE(arm9tdmi, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul)
! ARM_CORE(arm9e, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED, 9e)
! ARM_CORE(ep9312, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS, fastmul)
! ARM_CORE(strongarm, FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul)
! ARM_CORE(strongarm110, FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul)
! ARM_CORE(strongarm1100, FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul)
! ARM_CORE(strongarm1110, FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul)
/* V5 Architecture Processors */
! ARM_CORE(arm10tdmi, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5, fastmul)
! ARM_CORE(arm1020t, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5, fastmul)
! ARM_CORE(arm926ejs, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E, 9e)
! ARM_CORE(arm1026ejs, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E, 9e)
! ARM_CORE(xscale, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE, xscale)
! ARM_CORE(iwmmxt, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT, xscale)
/* V6 Architecture Processors */
! ARM_CORE(arm1136js, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J, 9e)
! ARM_CORE(arm1136jfs, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J | FL_VFPV2, 9e)
--- 57,87 ----
/* Doesn't have an external co-proc, but does have embedded fpa. */
ARM_CORE(arm7500fe, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul)
/* V4 Architecture Processors */
! ARM_CORE(arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB, fastmul)
! ARM_CORE(arm710t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB, fastmul)
! ARM_CORE(arm720t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB, fastmul)
! ARM_CORE(arm740t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB, fastmul)
! ARM_CORE(arm8, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED, fastmul)
! ARM_CORE(arm810, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED, fastmul)
! ARM_CORE(arm9, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul)
! ARM_CORE(arm920, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED, fastmul)
! ARM_CORE(arm920t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul)
! ARM_CORE(arm940t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul)
! ARM_CORE(arm9tdmi, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul)
! ARM_CORE(arm9e, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED, 9e)
! ARM_CORE(ep9312, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS, fastmul)
! ARM_CORE(strongarm, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul)
! ARM_CORE(strongarm110, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul)
! ARM_CORE(strongarm1100, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul)
! ARM_CORE(strongarm1110, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul)
/* V5 Architecture Processors */
! ARM_CORE(arm10tdmi, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5, fastmul)
! ARM_CORE(arm1020t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5, fastmul)
! ARM_CORE(arm926ejs, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E, 9e)
! ARM_CORE(arm1026ejs, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E, 9e)
! ARM_CORE(xscale, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE, xscale)
! ARM_CORE(iwmmxt, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT, xscale)
/* V6 Architecture Processors */
! ARM_CORE(arm1136js, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6, 9e)
! ARM_CORE(arm1136jfs, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 | FL_VFPV2, 9e)
Index: arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.303.2.12
diff -p -r1.303.2.12 arm.c
*** arm.c 7 Jan 2004 13:58:17 -0000 1.303.2.12
--- arm.c 8 Jan 2004 10:52:29 -0000
*************** int arm_structure_size_boundary = DEF
*** 288,294 ****
/* Bit values used to identify processor capabilities. */
#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
! #define FL_FAST_MULT (1 << 1) /* Fast multiply */
#define FL_MODE26 (1 << 2) /* 26-bit mode support */
#define FL_MODE32 (1 << 3) /* 32-bit mode support */
#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
--- 288,294 ----
/* Bit values used to identify processor capabilities. */
#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
! #define FL_ARCH3M (1 << 1) /* Extended multiply */
#define FL_MODE26 (1 << 2) /* 26-bit mode support */
#define FL_MODE32 (1 << 3) /* 32-bit mode support */
#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
*************** int arm_structure_size_boundary = DEF
*** 299,324 ****
#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
#define FL_XSCALE (1 << 10) /* XScale */
#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
! #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
! #define FL_ARCH6J (1 << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
/* The bits in this mask specify which
instructions we are allowed to generate. */
static unsigned long insn_flags = 0;
/* The bits in this mask specify which instruction scheduling options should
! be used. Note - there is an overlap with the FL_FAST_MULT. For some
! hardware we want to be able to generate the multiply instructions, but to
! tune as if they were not present in the architecture. */
static unsigned long tune_flags = 0;
/* The following are used in the arm.md file as equivalents to bits
in the above two flag variables. */
! /* Nonzero if this is an "M" variant of the processor. */
! int arm_fast_multiply = 0;
/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
int arm_arch4 = 0;
--- 299,323 ----
#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
#define FL_XSCALE (1 << 10) /* XScale */
#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
! #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
+ #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
+
/* The bits in this mask specify which
instructions we are allowed to generate. */
static unsigned long insn_flags = 0;
/* The bits in this mask specify which instruction scheduling options should
! be used. */
static unsigned long tune_flags = 0;
/* The following are used in the arm.md file as equivalents to bits
in the above two flag variables. */
! /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
! int arm_arch3m = 0;
/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
int arm_arch4 = 0;
*************** int arm_arch5 = 0;
*** 330,336 ****
int arm_arch5e = 0;
/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
! int arm_arch6j = 0;
/* Nonzero if this chip can benefit from load scheduling. */
int arm_ld_sched = 0;
--- 329,335 ----
int arm_arch5e = 0;
/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
! int arm_arch6 = 0;
/* Nonzero if this chip can benefit from load scheduling. */
int arm_ld_sched = 0;
*************** static const struct processors all_archi
*** 419,436 ****
{ "armv2", arm2, FL_CO_PROC | FL_MODE26 , NULL},
{ "armv2a", arm2, FL_CO_PROC | FL_MODE26 , NULL},
{ "armv3", arm6, FL_CO_PROC | FL_MODE26 | FL_MODE32 , NULL},
! { "armv3m", arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT , NULL},
! { "armv4", arm7tdmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 , NULL},
/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
implementations that support it, so we will leave it out for now. */
! { "armv4t", arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB , NULL},
! { "armv5", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
! { "armv5t", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
! { "armv5te", arm1026ejs, FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E , NULL},
! { "armv6", arm1136js, FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J , NULL},
! { "armv6j", arm1136js, FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J , NULL},
! { "ep9312", ep9312, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS , NULL},
! {"iwmmxt", iwmmxt, FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT , NULL},
{ NULL, arm_none, 0 , NULL}
};
--- 418,435 ----
{ "armv2", arm2, FL_CO_PROC | FL_MODE26 , NULL},
{ "armv2a", arm2, FL_CO_PROC | FL_MODE26 , NULL},
{ "armv3", arm6, FL_CO_PROC | FL_MODE26 | FL_MODE32 , NULL},
! { "armv3m", arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M , NULL},
! { "armv4", arm7tdmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 , NULL},
/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
implementations that support it, so we will leave it out for now. */
! { "armv4t", arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB , NULL},
! { "armv5", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
! { "armv5t", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
! { "armv5te", arm1026ejs, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E , NULL},
! { "armv6", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL},
! { "armv6j", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL},
! { "ep9312", ep9312, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS , NULL},
! {"iwmmxt", iwmmxt, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT , NULL},
{ NULL, arm_none, 0 , NULL}
};
*************** arm_override_options (void)
*** 786,805 ****
warning ("passing floating point arguments in fp regs not yet supported");
/* Initialize boolean versions of the flags, for use in the arm.md file. */
! arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
! arm_arch4 = (insn_flags & FL_ARCH4) != 0;
! arm_arch5 = (insn_flags & FL_ARCH5) != 0;
! arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
! arm_arch6j = (insn_flags & FL_ARCH6J) != 0;
! arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
!
! arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
! arm_is_strong = (tune_flags & FL_STRONG) != 0;
! thumb_code = (TARGET_ARM == 0);
! arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
! && !(tune_flags & FL_ARCH4))) != 0;
! arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
! arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
if (TARGET_IWMMXT && (! TARGET_ATPCS))
target_flags |= ARM_FLAG_ATPCS;
--- 785,804 ----
warning ("passing floating point arguments in fp regs not yet supported");
/* Initialize boolean versions of the flags, for use in the arm.md file. */
! arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
! arm_arch4 = (insn_flags & FL_ARCH4) != 0;
! arm_arch5 = (insn_flags & FL_ARCH5) != 0;
! arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
! arm_arch6 = (insn_flags & FL_ARCH6) != 0;
! arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
!
! arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
! arm_is_strong = (tune_flags & FL_STRONG) != 0;
! thumb_code = (TARGET_ARM == 0);
! arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
! && !(tune_flags & FL_ARCH4))) != 0;
! arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
! arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
if (TARGET_IWMMXT && (! TARGET_ATPCS))
target_flags |= ARM_FLAG_ATPCS;
*************** arm_rtx_costs_1 (rtx x, enum rtx_code co
*** 3459,3465 ****
abort ();
case TRUNCATE:
! if (arm_fast_multiply && mode == SImode
&& GET_CODE (XEXP (x, 0)) == LSHIFTRT
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
&& (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
--- 3458,3464 ----
abort ();
case TRUNCATE:
! if (arm_arch3m && mode == SImode
&& GET_CODE (XEXP (x, 0)) == LSHIFTRT
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
&& (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
Index: arm.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.h,v
retrieving revision 1.210.2.12
diff -p -r1.210.2.12 arm.h
*** arm.h 31 Dec 2003 22:55:48 -0000 1.210.2.12
--- arm.h 8 Jan 2004 10:52:29 -0000
*************** extern GTY(()) rtx aof_pic_label;
*** 274,279 ****
--- 274,280 ----
%{march=armv5t:-D__ARM_ARCH_5T__} \
%{march=armv5e:-D__ARM_ARCH_5E__} \
%{march=armv5te:-D__ARM_ARCH_5TE__} \
+ %{march=armv6:-D__ARM_ARCH6__} \
%{march=armv6j:-D__ARM_ARCH6J__} \
%{!march=*: \
%{mcpu=arm2:-D__ARM_ARCH_2__} \
*************** extern enum float_abi_type arm_float_abi
*** 681,701 ****
#define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
#endif
! /* Nonzero if the processor has a fast multiply insn, and one that does
! a 64-bit multiply of two 32-bit values. */
! extern int arm_fast_multiply;
! /* Nonzero if this chip supports the ARM Architecture 4 extensions */
extern int arm_arch4;
! /* Nonzero if this chip supports the ARM Architecture 5 extensions */
extern int arm_arch5;
! /* Nonzero if this chip supports the ARM Architecture 5E extensions */
extern int arm_arch5e;
! /* Nonzero if this chip supports the ARM Architecture 6 extensions */
! extern int arm_arch6j;
/* Nonzero if this chip can benefit from load scheduling. */
extern int arm_ld_sched;
--- 682,701 ----
#define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
#endif
! /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
! extern int arm_arch3m;
! /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
extern int arm_arch4;
! /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
extern int arm_arch5;
! /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
extern int arm_arch5e;
! /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
! extern int arm_arch6;
/* Nonzero if this chip can benefit from load scheduling. */
extern int arm_ld_sched;
Index: arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.145.2.11
diff -p -r1.145.2.11 arm.md
*** arm.md 7 Jan 2004 13:58:17 -0000 1.145.2.11
--- arm.md 8 Jan 2004 10:52:29 -0000
***************
*** 1175,1181 ****
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
(sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
(match_operand:DI 1 "s_register_operand" "0")))]
! "TARGET_ARM && arm_fast_multiply"
"smlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "insn" "smlal")
(set_attr "predicable" "yes")]
--- 1175,1181 ----
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
(sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
(match_operand:DI 1 "s_register_operand" "0")))]
! "TARGET_ARM && arm_arch3m"
"smlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "insn" "smlal")
(set_attr "predicable" "yes")]
***************
*** 1186,1192 ****
(mult:DI
(sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
! "TARGET_ARM && arm_fast_multiply"
"smull%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "smull")
(set_attr "predicable" "yes")]
--- 1186,1192 ----
(mult:DI
(sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
! "TARGET_ARM && arm_arch3m"
"smull%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "smull")
(set_attr "predicable" "yes")]
***************
*** 1197,1203 ****
(mult:DI
(zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
! "TARGET_ARM && arm_fast_multiply"
"umull%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "umull")
(set_attr "predicable" "yes")]
--- 1197,1203 ----
(mult:DI
(zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
! "TARGET_ARM && arm_arch3m"
"umull%?\\t%Q0, %R0, %1, %2"
[(set_attr "insn" "umull")
(set_attr "predicable" "yes")]
***************
*** 1212,1218 ****
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
(zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
(match_operand:DI 1 "s_register_operand" "0")))]
! "TARGET_ARM && arm_fast_multiply"
"umlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "insn" "umlal")
(set_attr "predicable" "yes")]
--- 1212,1218 ----
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
(zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
(match_operand:DI 1 "s_register_operand" "0")))]
! "TARGET_ARM && arm_arch3m"
"umlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "insn" "umlal")
(set_attr "predicable" "yes")]
***************
*** 1227,1233 ****
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&r,&r"))]
! "TARGET_ARM && arm_fast_multiply"
"smull%?\\t%3, %0, %2, %1"
[(set_attr "insn" "smull")
(set_attr "predicable" "yes")]
--- 1227,1233 ----
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&r,&r"))]
! "TARGET_ARM && arm_arch3m"
"smull%?\\t%3, %0, %2, %1"
[(set_attr "insn" "smull")
(set_attr "predicable" "yes")]
***************
*** 1242,1248 ****
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&r,&r"))]
! "TARGET_ARM && arm_fast_multiply"
"umull%?\\t%3, %0, %2, %1"
[(set_attr "insn" "umull")
(set_attr "predicable" "yes")]
--- 1242,1248 ----
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&r,&r"))]
! "TARGET_ARM && arm_arch3m"
"umull%?\\t%3, %0, %2, %1"
[(set_attr "insn" "umull")
(set_attr "predicable" "yes")]
***************
*** 3158,3164 ****
if (!s_register_operand (operands[1], HImode))
operands[1] = copy_to_mode_reg (HImode, operands[1]);
! if (arm_arch6j)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_ZERO_EXTEND (SImode, operands[1])));
--- 3158,3164 ----
if (!s_register_operand (operands[1], HImode))
operands[1] = copy_to_mode_reg (HImode, operands[1]);
! if (arm_arch6)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_ZERO_EXTEND (SImode, operands[1])));
***************
*** 3173,3179 ****
(define_insn "*thumb_zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=l")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
! "TARGET_THUMB && !arm_arch6j"
"*
rtx mem = XEXP (operands[1], 0);
--- 3173,3179 ----
(define_insn "*thumb_zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=l")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
! "TARGET_THUMB && !arm_arch6"
"*
rtx mem = XEXP (operands[1], 0);
***************
*** 3215,3221 ****
(define_insn "*thumb_zero_extendhisi2_v6"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))]
! "TARGET_THUMB && arm_arch6j"
"*
rtx mem;
--- 3215,3221 ----
(define_insn "*thumb_zero_extendhisi2_v6"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))]
! "TARGET_THUMB && arm_arch6"
"*
rtx mem;
***************
*** 3262,3268 ****
(define_insn "*arm_zero_extendhisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
! "TARGET_ARM && arm_arch4 && !arm_arch6j"
"ldr%?h\\t%0, %1"
[(set_attr "type" "load_byte")
(set_attr "predicable" "yes")
--- 3262,3268 ----
(define_insn "*arm_zero_extendhisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
! "TARGET_ARM && arm_arch4 && !arm_arch6"
"ldr%?h\\t%0, %1"
[(set_attr "type" "load_byte")
(set_attr "predicable" "yes")
***************
*** 3273,3279 ****
(define_insn "*arm_zero_extendhisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
! "TARGET_ARM && arm_arch6j"
"@
uxth%?\\t%0, %1
ldr%?h\\t%0, %1"
--- 3273,3279 ----
(define_insn "*arm_zero_extendhisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
! "TARGET_ARM && arm_arch6"
"@
uxth%?\\t%0, %1
ldr%?h\\t%0, %1"
***************
*** 3287,3293 ****
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (zero_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
(match_operand:SI 2 "s_register_operand" "r")))]
! "TARGET_ARM && arm_arch6j"
"uxtah%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift")
(set_attr "predicable" "yes")]
--- 3287,3293 ----
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (zero_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
(match_operand:SI 2 "s_register_operand" "r")))]
! "TARGET_ARM && arm_arch6"
"uxtah%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift")
(set_attr "predicable" "yes")]
***************
*** 3328,3334 ****
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
"TARGET_EITHER"
"
! if (!arm_arch6j && GET_CODE (operands[1]) != MEM)
{
if (TARGET_ARM)
{
--- 3328,3334 ----
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
"TARGET_EITHER"
"
! if (!arm_arch6 && GET_CODE (operands[1]) != MEM)
{
if (TARGET_ARM)
{
***************
*** 3366,3372 ****
(define_insn "*thumb_zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=l")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
! "TARGET_THUMB && !arm_arch6j"
"ldrb\\t%0, %1"
[(set_attr "length" "2")
(set_attr "type" "load_byte")
--- 3366,3372 ----
(define_insn "*thumb_zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=l")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
! "TARGET_THUMB && !arm_arch6"
"ldrb\\t%0, %1"
[(set_attr "length" "2")
(set_attr "type" "load_byte")
***************
*** 3376,3382 ****
(define_insn "*thumb_zero_extendqisi2_v6"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,m")))]
! "TARGET_THUMB && arm_arch6j"
"@
uxtb\\t%0, %1
ldrb\\t%0, %1"
--- 3376,3382 ----
(define_insn "*thumb_zero_extendqisi2_v6"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,m")))]
! "TARGET_THUMB && arm_arch6"
"@
uxtb\\t%0, %1
ldrb\\t%0, %1"
***************
*** 3388,3394 ****
(define_insn "*arm_zero_extendqisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
! "TARGET_ARM && !arm_arch6j"
"ldr%?b\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "load_byte")
(set_attr "predicable" "yes")
--- 3388,3394 ----
(define_insn "*arm_zero_extendqisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
! "TARGET_ARM && !arm_arch6"
"ldr%?b\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "load_byte")
(set_attr "predicable" "yes")
***************
*** 3399,3405 ****
(define_insn "*arm_zero_extendqisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
! "TARGET_ARM && arm_arch6j"
"@
uxtb%?\\t%0, %1
ldr%?b\\t%0, %1\\t%@ zero_extendqisi2"
--- 3399,3405 ----
(define_insn "*arm_zero_extendqisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
! "TARGET_ARM && arm_arch6"
"@
uxtb%?\\t%0, %1
ldr%?b\\t%0, %1\\t%@ zero_extendqisi2"
***************
*** 3413,3419 ****
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (zero_extend:SI (match_operand:QI 1 "s_register_operand" "r"))
(match_operand:SI 2 "s_register_operand" "r")))]
! "TARGET_ARM && arm_arch6j"
"uxtab%?\\t%0, %2, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "alu_shift")]
--- 3413,3419 ----
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (zero_extend:SI (match_operand:QI 1 "s_register_operand" "r"))
(match_operand:SI 2 "s_register_operand" "r")))]
! "TARGET_ARM && arm_arch6"
"uxtab%?\\t%0, %2, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "alu_shift")]
***************
*** 3476,3482 ****
if (!s_register_operand (operands[1], HImode))
operands[1] = copy_to_mode_reg (HImode, operands[1]);
! if (arm_arch6j)
{
if (TARGET_THUMB)
emit_insn (gen_thumb_extendhisi2 (operands[0], operands[1]));
--- 3476,3482 ----
if (!s_register_operand (operands[1], HImode))
operands[1] = copy_to_mode_reg (HImode, operands[1]);
! if (arm_arch6)
{
if (TARGET_THUMB)
emit_insn (gen_thumb_extendhisi2 (operands[0], operands[1]));
***************
*** 3496,3502 ****
[(set (match_operand:SI 0 "register_operand" "=l")
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
(clobber (match_scratch:SI 2 "=&l"))]
! "TARGET_THUMB && !arm_arch6j"
"*
{
rtx ops[4];
--- 3496,3502 ----
[(set (match_operand:SI 0 "register_operand" "=l")
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
(clobber (match_scratch:SI 2 "=&l"))]
! "TARGET_THUMB && !arm_arch6"
"*
{
rtx ops[4];
***************
*** 3561,3567 ****
[(set (match_operand:SI 0 "register_operand" "=l,l")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))
(clobber (match_scratch:SI 2 "=X,l"))]
! "TARGET_THUMB && arm_arch6j"
"*
{
rtx ops[4];
--- 3561,3567 ----
[(set (match_operand:SI 0 "register_operand" "=l,l")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))
(clobber (match_scratch:SI 2 "=X,l"))]
! "TARGET_THUMB && arm_arch6"
"*
{
rtx ops[4];
***************
*** 3663,3669 ****
(define_insn "*arm_extendhisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
! "TARGET_ARM && arm_arch4 && !arm_arch6j"
"ldr%?sh\\t%0, %1"
[(set_attr "type" "load_byte")
(set_attr "predicable" "yes")
--- 3663,3669 ----
(define_insn "*arm_extendhisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
! "TARGET_ARM && arm_arch4 && !arm_arch6"
"ldr%?sh\\t%0, %1"
[(set_attr "type" "load_byte")
(set_attr "predicable" "yes")
***************
*** 3674,3680 ****
(define_insn "*arm_extendhisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
! "TARGET_ARM && arm_arch6j"
"@
sxth%?\\t%0, %1
ldr%?sh\\t%0, %1"
--- 3674,3680 ----
(define_insn "*arm_extendhisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
! "TARGET_ARM && arm_arch6"
"@
sxth%?\\t%0, %1
ldr%?sh\\t%0, %1"
***************
*** 3688,3694 ****
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (sign_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
(match_operand:SI 2 "s_register_operand" "r")))]
! "TARGET_ARM && arm_arch6j"
"sxtah%?\\t%0, %2, %1"
)
--- 3688,3694 ----
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (sign_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
(match_operand:SI 2 "s_register_operand" "r")))]
! "TARGET_ARM && arm_arch6"
"sxtah%?\\t%0, %2, %1"
)
***************
*** 3819,3825 ****
if (!s_register_operand (operands[1], QImode))
operands[1] = copy_to_mode_reg (QImode, operands[1]);
! if (arm_arch6j)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_SIGN_EXTEND (SImode, operands[1])));
--- 3819,3825 ----
if (!s_register_operand (operands[1], QImode))
operands[1] = copy_to_mode_reg (QImode, operands[1]);
! if (arm_arch6)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_SIGN_EXTEND (SImode, operands[1])));
***************
*** 3836,3842 ****
(define_insn "*arm_extendqisi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
! "TARGET_ARM && arm_arch4 && !arm_arch6j"
"*
/* If the address is invalid, this will split the instruction into two. */
if (bad_signed_byte_operand (operands[1], VOIDmode))
--- 3836,3842 ----
(define_insn "*arm_extendqisi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
! "TARGET_ARM && arm_arch4 && !arm_arch6"
"*
/* If the address is invalid, this will split the instruction into two. */
if (bad_signed_byte_operand (operands[1], VOIDmode))
***************
*** 3853,3859 ****
(define_insn "*arm_extendqisi_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
! "TARGET_ARM && arm_arch6j"
"*
if (which_alternative == 0)
return \"sxtb%?\\t%0, %1\";
--- 3853,3859 ----
(define_insn "*arm_extendqisi_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
! "TARGET_ARM && arm_arch6"
"*
if (which_alternative == 0)
return \"sxtb%?\\t%0, %1\";
***************
*** 3875,3881 ****
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (sign_extend:SI (match_operand:QI 1 "s_register_operand" "r"))
(match_operand:SI 2 "s_register_operand" "r")))]
! "TARGET_ARM && arm_arch6j"
"sxtab%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift")
(set_attr "predicable" "yes")]
--- 3875,3881 ----
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (sign_extend:SI (match_operand:QI 1 "s_register_operand" "r"))
(match_operand:SI 2 "s_register_operand" "r")))]
! "TARGET_ARM && arm_arch6"
"sxtab%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift")
(set_attr "predicable" "yes")]
***************
*** 3917,3923 ****
(define_insn "*thumb_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "V,m")))]
! "TARGET_THUMB && !arm_arch6j"
"*
{
rtx ops[3];
--- 3917,3923 ----
(define_insn "*thumb_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "V,m")))]
! "TARGET_THUMB && !arm_arch6"
"*
{
rtx ops[3];
***************
*** 3996,4002 ****
(define_insn "*thumb_extendqisi2_v6"
[(set (match_operand:SI 0 "register_operand" "=l,l,l")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))]
! "TARGET_THUMB && arm_arch6j"
"*
{
rtx ops[3];
--- 3996,4002 ----
(define_insn "*thumb_extendqisi2_v6"
[(set (match_operand:SI 0 "register_operand" "=l,l,l")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))]
! "TARGET_THUMB && arm_arch6"
"*
{
rtx ops[3];
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