[patch] gcc: Fix comment typos. Follow spelling conventions.
Kazu Hirata
kazu@cs.umass.edu
Wed Feb 4 19:46:00 GMT 2004
Hi,
Committed as obvious.
Kazu Hirata
2004-02-04 Kazu Hirata <kazu@cs.umass.edu>
* config/alpha/alpha.c, config/arc/arc.c,
config/arm/arm-cores.def, config/arm/arm.c, config/arm/arm.h,
config/arm/arm1026ejs.md, config/arm/arm1136jfs.md,
config/arm/arm926ejs.md, config/arm/vfp.md, config/avr/avr.c,
config/c4x/c4x.c, config/cris/cris.c, config/frv/frv.md,
config/i386/i386.c, config/i386/i386.h, config/i386/i386.md,
config/ia64/ia64.c, config/ia64/unwind-ia64.c,
config/iq2000/iq2000.c, config/m32r/m32r.c,
config/mips/mips.c, config/mmix/mmix.c, config/mmix/mmix.h,
config/ns32k/ns32k.c, config/pa/pa.c, config/pdp11/pdp11.c,
config/rs6000/darwin-ldouble.c, config/rs6000/rs6000.c,
config/rs6000/rs6000.h, config/sparc/sparc.c,
config/vax/vax.c: Fix comment typos. Follow spelling
conventions.
Index: alpha/alpha.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.c,v
retrieving revision 1.349
diff -u -r1.349 alpha.c
--- alpha/alpha.c 4 Feb 2004 12:22:33 -0000 1.349
+++ alpha/alpha.c 4 Feb 2004 19:41:34 -0000
@@ -2112,7 +2112,7 @@
*total = 0;
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case CONST_DOUBLE:
if (x == CONST0_RTX (mode))
@@ -2170,7 +2170,7 @@
*total = COSTS_N_INSNS (1);
return false;
}
- /* FALLTHRU */
+ /* Fall through. */
case ASHIFTRT:
case LSHIFTRT:
@@ -2206,7 +2206,7 @@
*total = COSTS_N_INSNS (1);
return false;
}
- /* FALLTHRU */
+ /* Fall through. */
case ABS:
if (! float_mode_p)
@@ -2214,7 +2214,7 @@
*total = COSTS_N_INSNS (1) + alpha_rtx_cost_data[alpha_cpu].int_cmov;
return false;
}
- /* FALLTHRU */
+ /* Fall through. */
case FLOAT:
case UNSIGNED_FLOAT:
@@ -3275,7 +3275,7 @@
case NE:
if (!fp_p && op1 == const0_rtx)
break;
- /* FALLTHRU */
+ /* Fall through. */
case ORDERED:
cmp_code = reverse_condition (code);
@@ -3708,7 +3708,7 @@
case VOIDmode:
if (GET_CODE (operands[i]) != CONST_INT)
abort ();
- /* FALLTHRU */
+ /* Fall through. */
case DImode:
reg = gen_rtx_REG (DImode, regno);
regno += 1;
@@ -6081,7 +6081,7 @@
case MODE_INT:
/* Do the same thing as PROMOTE_MODE. */
mode = DImode;
- /* FALLTHRU */
+ /* Fall through. */
case MODE_COMPLEX_INT:
case MODE_VECTOR_INT:
Index: arc/arc.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arc/arc.c,v
retrieving revision 1.48
diff -u -r1.48 arc.c
--- arc/arc.c 26 Jan 2004 23:22:51 -0000 1.48
+++ arc/arc.c 4 Feb 2004 19:41:36 -0000
@@ -834,7 +834,7 @@
*total = 0;
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case CONST:
case LABEL_REF:
Index: arm/arm-cores.def
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm-cores.def,v
retrieving revision 1.2
diff -u -r1.2 arm-cores.def
--- arm/arm-cores.def 3 Feb 2004 14:45:44 -0000 1.2
+++ arm/arm-cores.def 4 Feb 2004 19:41:36 -0000
@@ -27,7 +27,7 @@
rather than a string constant. The FLAGS are the bitwise-or of the
traits that apply to that core.
- If you update this table, you must update the "tune" attribue in
+ If you update this table, you must update the "tune" attribute in
arm.md. */
ARM_CORE(arm2, FL_CO_PROC | FL_MODE26, slowmul)
Index: arm/arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.327
diff -u -r1.327 arm.c
--- arm/arm.c 3 Feb 2004 14:44:10 -0000 1.327
+++ arm/arm.c 4 Feb 2004 19:41:42 -0000
@@ -3596,7 +3596,7 @@
}
}
-/* RTX costs for cores with a slow MUL implimentation. */
+/* RTX costs for cores with a slow MUL implementation. */
static bool
arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
@@ -4424,7 +4424,7 @@
|| reg_mentioned_p (virtual_stack_vars_rtx, op)))
return FALSE;
- /* Constants are converted into offets from labels. */
+ /* Constants are converted into offsets from labels. */
if (GET_CODE (op) == MEM)
{
rtx ind;
@@ -9186,7 +9186,7 @@
not have base+offset addressing modes, so we use IP to
hold the address. Each block requires nregs*2+1 words. */
start_reg = FIRST_VFP_REGNUM;
- /* Cound how many blocks of registers need saving. */
+ /* Count how many blocks of registers need saving. */
for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
{
if ((!regs_ever_live[reg] || call_used_regs[reg])
@@ -12449,7 +12449,7 @@
/* Emit code to push or pop registers to or from the stack. F is the
assembly file. MASK is the registers to push or pop. PUSH is
- non-zero if we should push, and zero if we should pop. For debugging
+ nonzero if we should push, and zero if we should pop. For debugging
output, if pushing, adjust CFA_OFFSET by the amount of space added
to the stack. REAL_REGS should have the same number of bits set as
MASK, and will be used instead (in the same order) to describe which
@@ -14132,7 +14132,7 @@
*pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
}
-/* Return non-zero if the CONSUMER instruction (a store) does not need
+/* Return nonzero if the CONSUMER instruction (a store) does not need
PRODUCER's value to calculate the address. */
int
@@ -14155,7 +14155,7 @@
return !reg_overlap_mentioned_p (value, addr);
}
-/* Return non-zero if the CONSUMER instruction (an ALU op) does not
+/* Return nonzero if the CONSUMER instruction (an ALU op) does not
have an early register shift value or amount dependency on the
result of PRODUCER. */
@@ -14187,7 +14187,7 @@
return !reg_overlap_mentioned_p (value, early_op);
}
-/* Return non-zero if the CONSUMER instruction (an ALU op) does not
+/* Return nonzero if the CONSUMER instruction (an ALU op) does not
have an early register shift value dependency on the result of
PRODUCER. */
@@ -14220,7 +14220,7 @@
return !reg_overlap_mentioned_p (value, early_op);
}
-/* Return non-zero if the CONSUMER (a mul or mac op) does not
+/* Return nonzero if the CONSUMER (a mul or mac op) does not
have an early register mult dependency on the result of
PRODUCER. */
Index: arm/arm.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.h,v
retrieving revision 1.218
diff -u -r1.218 arm.h
--- arm/arm.h 3 Feb 2004 14:44:10 -0000 1.218
+++ arm/arm.h 4 Feb 2004 19:41:44 -0000
@@ -136,7 +136,7 @@
extern int target_flags;
/* The floating point mode. */
extern const char *target_fpu_name;
-/* For backwards compatability. */
+/* For backwards compatibility. */
extern const char *target_fpe_name;
/* Whether to use floating point hardware. */
extern const char *target_float_abi_name;
@@ -672,7 +672,7 @@
/* Default floating point architecture. Override in sub-target if
necessary.
- FIXME: Is this still neccessary/desirable? Do we want VFP chips to
+ FIXME: Is this still necessary/desirable? Do we want VFP chips to
default to VFP unless overridden by a subtarget? If so it would be best
to remove these definitions. It also assumes there is only one cpu model
with a Maverick fpu. */
@@ -1379,7 +1379,7 @@
#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
/* FPA registers can't do subreg as all values are reformatted to internal
- precision. VFP registers may only be accesed in the mode they
+ precision. VFP registers may only be accessed in the mode they
were set. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
Index: arm/arm1026ejs.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm1026ejs.md,v
retrieving revision 1.2
diff -u -r1.2 arm1026ejs.md
--- arm/arm1026ejs.md 3 Feb 2004 14:45:44 -0000 1.2
+++ arm/arm1026ejs.md 4 Feb 2004 19:41:44 -0000
@@ -141,7 +141,7 @@
;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
;; the execute stage for five iterations in order to set the flags.
-;; The value result is vailable after four iterations.
+;; The value result is available after four iterations.
(define_insn_reservation "mult6" 4
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "insn" "umulls,umlals,smulls,smlals"))
@@ -185,7 +185,7 @@
;; base address is 64-bit aligned; if it is not, an additional cycle
;; is required. This model assumes that the address is always 64-bit
;; aligned. Because the processor can load two registers per cycle,
-;; that assumption means that we use the same instruction rservations
+;; that assumption means that we use the same instruction reservations
;; for loading 2k and 2k - 1 registers.
;;
;; The ALU pipeline is stalled until the completion of the last memory
@@ -233,7 +233,7 @@
"nothing")
;; The latency for a call is not predictable. Therefore, we use 32 as
-;; roughly equivalent to postive infinity.
+;; roughly equivalent to positive infinity.
(define_insn_reservation "call_op" 32
(and (eq_attr "tune" "arm1026ejs")
Index: arm/arm1136jfs.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm1136jfs.md,v
retrieving revision 1.2
diff -u -r1.2 arm1136jfs.md
--- arm/arm1136jfs.md 3 Feb 2004 14:45:44 -0000 1.2
+++ arm/arm1136jfs.md 4 Feb 2004 19:41:44 -0000
@@ -56,7 +56,7 @@
;;
;; - A 4-stage LSU pipeline. It has address generation, data cache (1),
;; data cache (2), and writeback stages. (Note that this pipeline,
-;; including the writeback stage, is independant from the ALU & LSU pipes.)
+;; including the writeback stage, is independent from the ALU & LSU pipes.)
(define_cpu_unit "e_1,e_2,e_3,e_wb" "arm1136jfs") ; ALU and MAC
; e_1 = Sh/Mac1, e_2 = ALU/Mac2, e_3 = SAT/Mac3
@@ -336,7 +336,7 @@
"arm_no_early_store_addr_dep")
;; An alu op can start sooner after a load, if that alu op does not
-;; have an early register dependancy on the load
+;; have an early register dependency on the load
(define_bypass 2 "11_load1"
"11_alu_op")
(define_bypass 2 "11_load1"
Index: arm/arm926ejs.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm926ejs.md,v
retrieving revision 1.2
diff -u -r1.2 arm926ejs.md
--- arm/arm926ejs.md 3 Feb 2004 14:45:44 -0000 1.2
+++ arm/arm926ejs.md 4 Feb 2004 19:41:44 -0000
@@ -180,7 +180,7 @@
"nothing")
;; The latency for a call is not predictable. Therefore, we use 32 as
-;; roughly equivalent to postive infinity.
+;; roughly equivalent to positive infinity.
(define_insn_reservation "9_call_op" 32
(and (eq_attr "tune" "arm926ejs")
Index: arm/vfp.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/vfp.md,v
retrieving revision 1.2
diff -u -r1.2 vfp.md
--- arm/vfp.md 3 Feb 2004 14:45:44 -0000 1.2
+++ arm/vfp.md 4 Feb 2004 19:41:44 -0000
@@ -42,10 +42,10 @@
;; second memory stage for loads.
;; We do not model Write-After-Read hazards.
-;; We do not do write scheduling with the arm core, so it is only neccessary
-;; to model the first stage of each pieline
+;; We do not do write scheduling with the arm core, so it is only necessary
+;; to model the first stage of each pipeline
;; ??? Need to model LS pipeline properly for load/store multiple?
-;; We do not model fmstat properly. This could be done by modeiling pipelines
+;; We do not model fmstat properly. This could be done by modeling pipelines
;; properly and defining an absence set between a dummy fmstat unit and all
;; other vfp units.
@@ -58,7 +58,7 @@
;; The VFP "type" attributes differ from those used in the FPA model.
;; ffarith Fast floating point insns, eg. abs, neg, cpy, cmp.
;; farith Most arithmetic insns.
-;; fmul Double preision multiply.
+;; fmul Double precision multiply.
;; fdivs Single precision sqrt or division.
;; fdivd Double precision sqrt or division.
;; f_load Floating point load from memory.
@@ -104,12 +104,12 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;; Insn pattersn
+;; Insn pattern
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; SImode moves
;; ??? For now do not allow loading constants into vfp regs. This causes
-;; problems because small sonstants get converted into adds.
+;; problems because small constants get converted into adds.
(define_insn "*arm_movsi_vfp"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r ,m,!w,r,!w,!w, U")
(match_operand:SI 1 "general_operand" "rI,K,mi,r,r,!w,!w,Ui,!w"))]
@@ -738,7 +738,7 @@
;; fldm*
;; fstm*
;; fmdhr et al (VFPv1)
-;; Support for xD (single precisio only) variants.
+;; Support for xD (single precision only) variants.
;; fmrrs, fmsrr
;; fuito*
;; ftoui*
Index: avr/avr.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/avr/avr.c,v
retrieving revision 1.112
diff -u -r1.112 avr.c
--- avr/avr.c 1 Feb 2004 21:21:34 -0000 1.112
+++ avr/avr.c 4 Feb 2004 19:41:46 -0000
@@ -4825,7 +4825,7 @@
*total = 2;
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case CONST:
case LABEL_REF:
Index: c4x/c4x.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/c4x/c4x.c,v
retrieving revision 1.144
diff -u -r1.144 c4x.c
--- c4x/c4x.c 3 Feb 2004 06:43:43 -0000 1.144
+++ c4x/c4x.c 4 Feb 2004 19:41:48 -0000
@@ -3475,7 +3475,7 @@
return;
}
}
- /* Fallthrough. */
+ /* Fall through. */
default:
fatal_insn ("invalid indirect (S) memory address", op);
@@ -3992,7 +3992,7 @@
/* When the shift count is greater than 32 then the result
can be implementation dependent. We truncate the result to
fit in 5 bits so that we do not emit invalid code when
- optimising---such as trying to generate lhu2 with 20021124-1.c. */
+ optimizing---such as trying to generate lhu2 with 20021124-1.c. */
if (((code == ASHIFTRT || code == LSHIFTRT || code == ASHIFT)
&& (GET_CODE (operands[2]) == CONST_INT))
&& INTVAL (operands[2]) > (GET_MODE_BITSIZE (mode) - 1))
Index: cris/cris.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/cris/cris.c,v
retrieving revision 1.49
diff -u -r1.49 cris.c
--- cris/cris.c 26 Jan 2004 15:54:45 -0000 1.49
+++ cris/cris.c 4 Feb 2004 19:41:49 -0000
@@ -1308,7 +1308,7 @@
switch (code)
{
case 'b':
- /* Print the unsigned supplied integer as if it was signed
+ /* Print the unsigned supplied integer as if it were signed
and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
if (GET_CODE (x) != CONST_INT
|| ! CONST_OK_FOR_LETTER_P (INTVAL (x), 'O'))
@@ -1734,7 +1734,7 @@
= regs_ever_live[CRIS_SRP_REGNUM]
|| cfun->machine->needs_return_address_on_stack != 0;
- /* Here we act as if the frame-pointer is needed. */
+ /* Here we act as if the frame-pointer were needed. */
int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
if (fromreg == ARG_POINTER_REGNUM
Index: frv/frv.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/frv/frv.md,v
retrieving revision 1.10
diff -u -r1.10 frv.md
--- frv/frv.md 3 Feb 2004 06:43:45 -0000 1.10
+++ frv/frv.md 4 Feb 2004 19:41:51 -0000
@@ -309,8 +309,8 @@
;; Type: the name of the define_attr type
;; Conditions: "yes" if conditional variants are available
-;; FR500: Fujitsu's categorisation for the FR500
-;; FR400: Fujitsu's categorisation for the FR400 (but see below).
+;; FR500: Fujitsu's categorization for the FR500
+;; FR400: Fujitsu's categorization for the FR400 (but see below).
;; On the FR400, media instructions are divided into 2 broad categories.
;; Category 1 instructions can execute in either the M0 or M1 unit and can
@@ -502,7 +502,7 @@
(define_cpu_unit "sl2_i1, sl2_fm1, sl2_b0, sl2_b1" "nodiv")
(define_cpu_unit "sl3_fm1, sl3_b0, sl3_b1" "nodiv")
-;; The following describes conlicts by slots
+;; The following describes conflicts by slots
;; slot0
(exclusion_set "sl0_i0" "sl0_fm0,sl0_b0,sl0_c")
(exclusion_set "sl0_fm0" "sl0_b0,sl0_c")
@@ -523,7 +523,7 @@
(exclusion_set "sl3_fm1" "sl3_b0,sl3_b1")
(exclusion_set "sl3_b0" "sl3_b1")
-;; The following describes conlicts by units
+;; The following describes conflicts by units
;; fm0
(exclusion_set "sl0_fm0" "sl1_fm0")
@@ -3337,7 +3337,7 @@
;; "iordi3 %0,%1,%2"
;; [(set_attr "length" "4")])
-;; Excludive OR, 64 bit integers
+;; Exclusive OR, 64 bit integers
;; (define_insn "xordi3"
;; [(set (match_operand:DI 0 "register_operand" "=r")
;; (xor:DI (match_operand:DI 1 "register_operand" "%r")
Index: i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.643
diff -u -r1.643 i386.c
--- i386/i386.c 3 Feb 2004 05:39:56 -0000 1.643
+++ i386/i386.c 4 Feb 2004 19:41:58 -0000
@@ -2573,7 +2573,7 @@
case BLKmode:
if (bytes < 0)
break;
- /* FALLTHRU */
+ /* Fall through. */
case DImode:
case SImode:
case HImode:
@@ -5836,7 +5836,7 @@
default:
return false;
}
- /* FALLTHRU */
+ /* Fall through. */
case SYMBOL_REF:
case LABEL_REF:
@@ -6712,7 +6712,7 @@
case LABEL_REF:
x = XEXP (x, 0);
- /* FALLTHRU */
+ /* Fall through. */
case CODE_LABEL:
ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
assemble_name (asm_out_file, buf);
@@ -7100,13 +7100,13 @@
fputs ("st(0)", file);
break;
}
- /* FALLTHRU */
+ /* Fall through. */
case 8:
case 4:
case 12:
if (! ANY_FP_REG_P (x))
putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
- /* FALLTHRU */
+ /* Fall through. */
case 16:
case 2:
normal:
@@ -8630,15 +8630,15 @@
case CCmode:
if (req_mode == CCGCmode)
return 0;
- /* FALLTHRU */
+ /* Fall through. */
case CCGCmode:
if (req_mode == CCGOCmode || req_mode == CCNOmode)
return 0;
- /* FALLTHRU */
+ /* Fall through. */
case CCGOCmode:
if (req_mode == CCZmode)
return 0;
- /* FALLTHRU */
+ /* Fall through. */
case CCZmode:
break;
@@ -14653,7 +14653,7 @@
case HImode:
case SImode:
operand = gen_lowpart (DImode, operand);
- /* FALLTHRU */
+ /* Fall through. */
case DImode:
emit_insn (
gen_rtx_SET (VOIDmode,
@@ -14693,7 +14693,7 @@
/* It is better to store HImodes as SImodes. */
if (!TARGET_PARTIAL_REG_STALL)
operand = gen_lowpart (SImode, operand);
- /* FALLTHRU */
+ /* Fall through. */
case SImode:
emit_insn (
gen_rtx_SET (VOIDmode,
@@ -15058,7 +15058,7 @@
return false;
}
}
- /* FALLTHRU */
+ /* Fall through. */
case ROTATE:
case ASHIFTRT:
@@ -15166,7 +15166,7 @@
return true;
}
}
- /* FALLTHRU */
+ /* Fall through. */
case MINUS:
if (FLOAT_MODE_P (mode))
@@ -15174,7 +15174,7 @@
*total = COSTS_N_INSNS (ix86_cost->fadd);
return false;
}
- /* FALLTHRU */
+ /* Fall through. */
case AND:
case IOR:
@@ -15188,7 +15188,7 @@
<< (GET_MODE (XEXP (x, 1)) != DImode)));
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case NEG:
if (FLOAT_MODE_P (mode))
@@ -15196,7 +15196,7 @@
*total = COSTS_N_INSNS (ix86_cost->fchs);
return false;
}
- /* FALLTHRU */
+ /* Fall through. */
case NOT:
if (!TARGET_64BIT && mode == DImode)
Index: i386/i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.370
diff -u -r1.370 i386.h
--- i386/i386.h 31 Jan 2004 18:42:55 -0000 1.370
+++ i386/i386.h 4 Feb 2004 19:42:00 -0000
@@ -580,7 +580,7 @@
{ \
case '3': \
builtin_define ("__tune_pentium3__"); \
- /* FALLTHRU */ \
+ /* Fall through. */ \
case '2': \
builtin_define ("__tune_pentium2__"); \
break; \
Index: i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.507
diff -u -r1.507 i386.md
--- i386/i386.md 3 Feb 2004 05:39:57 -0000 1.507
+++ i386/i386.md 4 Feb 2004 19:42:05 -0000
@@ -1955,7 +1955,7 @@
case TYPE_SSEMOV:
if (get_attr_mode (insn) == MODE_TI)
return "movdqa\t{%1, %0|%0, %1}";
- /* FALLTHRU */
+ /* Fall through. */
case TYPE_MMXMOV:
/* Moves from and into integer register is done using movd opcode with
REX prefix. */
@@ -2005,7 +2005,7 @@
case TYPE_SSEMOV:
if (get_attr_mode (insn) == MODE_TI)
return "movdqa\t{%1, %0|%0, %1}";
- /* FALLTHRU */
+ /* Fall through. */
case TYPE_MMXMOV:
return "movq\t{%1, %0|%0, %1}";
case TYPE_MULTI:
Index: ia64/ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v
retrieving revision 1.269
diff -u -r1.269 ia64.c
--- ia64/ia64.c 3 Feb 2004 06:43:46 -0000 1.269
+++ ia64/ia64.c 4 Feb 2004 19:42:09 -0000
@@ -425,7 +425,7 @@
|| GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF)
break;
op = XEXP (XEXP (op, 0), 0);
- /* FALLTHRU */
+ /* Fall through. */
case SYMBOL_REF:
if (CONSTANT_POOL_ADDRESS_P (op))
@@ -5299,7 +5299,7 @@
case SUBREG:
x = SUBREG_REG (x);
- /* FALLTHRU */
+ /* Fall through. */
case REG:
if (REGNO (x) == AR_UNAT_REGNUM)
{
@@ -5550,7 +5550,7 @@
need_barrier = 1;
break;
}
- /* FALLTHRU */
+ /* Fall through. */
case INSN:
if (GET_CODE (PATTERN (insn)) == USE
Index: ia64/unwind-ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/unwind-ia64.c,v
retrieving revision 1.21
diff -u -r1.21 unwind-ia64.c
--- ia64/unwind-ia64.c 19 Dec 2003 14:00:51 -0000 1.21
+++ ia64/unwind-ia64.c 4 Feb 2004 19:42:10 -0000
@@ -1614,7 +1614,7 @@
*nat = 1;
return;
}
- /* FALLTHRU */
+ /* Fall through. */
case UNW_NAT_NONE:
dummy_nat = 0;
Index: iq2000/iq2000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/iq2000/iq2000.c,v
retrieving revision 1.11
diff -u -r1.11 iq2000.c
--- iq2000/iq2000.c 2 Feb 2004 15:18:19 -0000 1.11
+++ iq2000/iq2000.c 4 Feb 2004 19:42:11 -0000
@@ -2860,7 +2860,7 @@
char *c;
c = strchr (buffer, '\0');
- /* Generate the reversed comparision. This takes four
+ /* Generate the reversed comparison. This takes four
bytes. */
if (float_p)
sprintf (c, "b%s\t%%Z2%s",
Index: m32r/m32r.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m32r/m32r.c,v
retrieving revision 1.84
diff -u -r1.84 m32r.c
--- m32r/m32r.c 2 Feb 2004 06:31:02 -0000 1.84
+++ m32r/m32r.c 4 Feb 2004 19:42:13 -0000
@@ -1689,7 +1689,7 @@
*total = 0;
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case CONST:
case LABEL_REF:
Index: mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.375
diff -u -r1.375 mips.c
--- mips/mips.c 3 Feb 2004 22:38:30 -0000 1.375
+++ mips/mips.c 4 Feb 2004 19:42:17 -0000
@@ -1026,7 +1026,7 @@
stack pointer (which needs the restriction) or the hard frame
pointer (which doesn't).
- All in all, it seems more consitent to only enforce this restriction
+ All in all, it seems more consistent to only enforce this restriction
during and after reload. */
if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
Index: mmix/mmix.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mmix/mmix.c,v
retrieving revision 1.58
diff -u -r1.58 mmix.c
--- mmix/mmix.c 3 Feb 2004 06:43:51 -0000 1.58
+++ mmix/mmix.c 4 Feb 2004 19:42:19 -0000
@@ -2455,7 +2455,7 @@
|| (GET_CODE (XEXP (op, 1)) == CONST_DOUBLE
&& GET_MODE (XEXP (op, 1)) == VOIDmode)))
return 1;
- /* FALLTHROUGH */
+ /* Fall through. */
default:
return address_operand (op, mode);
}
Index: mmix/mmix.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mmix/mmix.h,v
retrieving revision 1.59
diff -u -r1.59 mmix.h
--- mmix/mmix.h 25 Jan 2004 17:28:19 -0000 1.59
+++ mmix/mmix.h 4 Feb 2004 19:42:19 -0000
@@ -174,7 +174,7 @@
address register) without having to know the specific register or the
specific offset. The setback is that there's a limited number of
registers, and you'll not find out until link time whether you
- should've compiled with -mno-base-addresses. */
+ should have compiled with -mno-base-addresses. */
#define TARGET_MASK_BASE_ADDRESSES 128
/* FIXME: Get rid of this one. */
Index: ns32k/ns32k.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ns32k/ns32k.c,v
retrieving revision 1.43
diff -u -r1.43 ns32k.c
--- ns32k/ns32k.c 3 Feb 2004 06:43:53 -0000 1.43
+++ ns32k/ns32k.c 4 Feb 2004 19:42:20 -0000
@@ -598,7 +598,7 @@
case MULT:
cost += 2;
- /* FALLTHRU */
+ /* Fall through. */
case PLUS:
cost += ns32k_address_cost (XEXP (operand, 0));
cost += ns32k_address_cost (XEXP (operand, 1));
Index: pa/pa.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.c,v
retrieving revision 1.240
diff -u -r1.240 pa.c
--- pa/pa.c 30 Jan 2004 23:16:15 -0000 1.240
+++ pa/pa.c 4 Feb 2004 19:42:24 -0000
@@ -1432,7 +1432,7 @@
*total = COSTS_N_INSNS (14);
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case UDIV:
case MOD:
Index: pdp11/pdp11.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pdp11/pdp11.c,v
retrieving revision 1.36
diff -u -r1.36 pdp11.c
--- pdp11/pdp11.c 3 Feb 2004 17:36:02 -0000 1.36
+++ pdp11/pdp11.c 4 Feb 2004 19:42:25 -0000
@@ -1084,7 +1084,7 @@
*total = 0;
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case CONST:
case LABEL_REF:
Index: rs6000/darwin-ldouble.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/darwin-ldouble.c,v
retrieving revision 1.3
diff -u -r1.3 darwin-ldouble.c
--- rs6000/darwin-ldouble.c 12 Jan 2004 18:37:40 -0000 1.3
+++ rs6000/darwin-ldouble.c 4 Feb 2004 19:42:25 -0000
@@ -103,7 +103,7 @@
c = t;
}
- /* Thanks to commutivity, sum is invariant w.r.t. the next
+ /* Thanks to commutativity, sum is invariant w.r.t. the next
conditional exchange. */
tau = d + c;
Index: rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.589
diff -u -r1.589 rs6000.c
--- rs6000/rs6000.c 4 Feb 2004 12:22:35 -0000 1.589
+++ rs6000/rs6000.c 4 Feb 2004 19:42:31 -0000
@@ -8974,7 +8974,7 @@
case 'Q':
if (TARGET_MFCRF)
fputc (',',file);
- /* FALLTHRU */
+ /* Fall through. */
else
return;
@@ -15581,7 +15581,7 @@
*total = COSTS_N_INSNS (2);
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case UDIV:
case UMOD:
Index: rs6000/rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.309
diff -u -r1.309 rs6000.h
--- rs6000/rs6000.h 30 Jan 2004 23:16:18 -0000 1.309
+++ rs6000/rs6000.h 4 Feb 2004 19:42:33 -0000
@@ -1437,7 +1437,7 @@
: (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
: 0)
-/* Defining, which contraints are memory contraints. Tells reload,
+/* Define which constraints are memory constraints. Tell reload
that any memory address can be reloaded by copying the
memory address into a base register if required. */
Index: sparc/sparc.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.c,v
retrieving revision 1.286
diff -u -r1.286 sparc.c
--- sparc/sparc.c 4 Feb 2004 19:02:16 -0000 1.286
+++ sparc/sparc.c 4 Feb 2004 19:42:37 -0000
@@ -8440,7 +8440,7 @@
*total = 0;
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case HIGH:
*total = 2;
Index: vax/vax.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/vax/vax.c,v
retrieving revision 1.53
diff -u -r1.53 vax.c
--- vax/vax.c 26 Jan 2004 00:05:38 -0000 1.53
+++ vax/vax.c 4 Feb 2004 19:42:37 -0000
@@ -557,7 +557,7 @@
return 1;
if (outer_code == PLUS && (unsigned HOST_WIDE_INT) -INTVAL (x) <= 077)
return 1;
- /* FALLTHRU */
+ /* Fall through. */
case CONST:
case LABEL_REF:
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