[committed] mips.md macroisation (20/n)
Richard Sandiford
rsandifo@redhat.com
Sun Aug 29 13:17:00 GMT 2004
Part 20 of the mips.md macroisation process. This patch handles the
floating-point operations for which V2SF is defined. Everything but
multiplication uses a single template for SF, DF and V2SF; I decided
to keep mulv2sf separate since it doesn't need the VR4300 workarounds.
There should only be one behavioural change: the V2SF madd/msub/nmadd/nmsub
patterns can now be controlled with -mfused-madd, just like the scalar
versions.
Bootstrapped & regression tested on mips-sgi-irix6.5. There should
be no behavioural change. Applied to head.
Richard
* config/mips/mips.md (ANYF, SCALARF): New mode macros.
(loadx, storex, fmt, UNITMODE): New mode attributes.
(add{sf,df,v2sf}3, sub{sf,df,v2sf}3): Redefine using :ANYF.
(mul[sd]f3): Redefine using :SCALARF.
(*mul[sd]f3): Renamed from mul[sd]f3_internal. Use :SCALARF.
(*mul[sd]3_r4300): Likewise mul[sd]f3_r4300.
(*m{add,sub}{sf,df,v2sf}3): Name formerly unnamed patterns. Use :ANYF.
Check TARGET_FUSED_MADD for V2SF too.
(*nm{add,sub}{sf,df,v2sf}3{,_fastmath}): Likewise, except v2sf patterns
were already named.
(abs{sf,df,v2sf}3, neg{sf,df,v2sf}3): Redefine using :ANYF.
(*[sl][wd]xc1_[sd]i): Redefine using :ANYF.
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.292
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.292 mips.md
*** config/mips/mips.md 29 Aug 2004 10:01:28 -0000 1.292
--- config/mips/mips.md 29 Aug 2004 11:32:46 -0000
*************** (define_mode_macro P [(SI "Pmode == SImo
*** 361,366 ****
--- 361,376 ----
;; conditional-move-type condition is needed.
(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
+ ;; This mode macro allows :ANYF to be used wherever a scalar or vector
+ ;; floating-point mode is allowed.
+ (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
+ (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
+
+ ;; Like ANYF, but only applies to scalar modes.
+ (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
+
;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr d [(SI "") (DI "d")])
*************** (define_mode_attr d [(SI "") (DI "d")])
*** 369,374 ****
--- 379,388 ----
(define_mode_attr load [(SI "lw") (DI "ld")])
(define_mode_attr store [(SI "sw") (DI "sd")])
+ ;; Similarly for MIPS IV indexed FPR loads and stores.
+ (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1")])
+ (define_mode_attr storex [(SF "swxc1") (DF "sdxc1")])
+
;; The unextended ranges of the MIPS16 addiu and daddiu instructions
;; are different. Some forms of unextended addiu have an 8-bit immediate
;; field but the equivalent daddiu has only a 5-bit field.
*************** (define_mode_attr si8_di5 [(SI "8") (DI
*** 378,383 ****
--- 392,404 ----
;; a given mode.
(define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
+ ;; This attribute gives the format suffix for floating-point operations.
+ (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
+
+ ;; This attribute gives the upper-case mode name for one unit of a
+ ;; floating-point mode.
+ (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
+
;; This code macro allows all branch instructions to be generated from
;; a single define_expand template.
(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
*************** (define_insn "*conditional_trap<mode>"
*** 517,548 ****
;; ....................
;;
! (define_insn "adddf3"
! [(set (match_operand:DF 0 "register_operand" "=f")
! (plus:DF (match_operand:DF 1 "register_operand" "f")
! (match_operand:DF 2 "register_operand" "f")))]
! "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
! "add.d\t%0,%1,%2"
! [(set_attr "type" "fadd")
! (set_attr "mode" "DF")])
!
! (define_insn "addsf3"
! [(set (match_operand:SF 0 "register_operand" "=f")
! (plus:SF (match_operand:SF 1 "register_operand" "f")
! (match_operand:SF 2 "register_operand" "f")))]
! "TARGET_HARD_FLOAT"
! "add.s\t%0,%1,%2"
! [(set_attr "type" "fadd")
! (set_attr "mode" "SF")])
!
! (define_insn "addv2sf3"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (plus:V2SF (match_operand:V2SF 1 "register_operand" "f")
! (match_operand:V2SF 2 "register_operand" "f")))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "add.ps\t%0,%1,%2"
[(set_attr "type" "fadd")
! (set_attr "mode" "SF")])
(define_expand "add<mode>3"
[(set (match_operand:GPR 0 "register_operand")
--- 538,551 ----
;; ....................
;;
! (define_insn "add<mode>3"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
! (match_operand:ANYF 2 "register_operand" "f")))]
! ""
! "add.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
! (set_attr "mode" "<UNITMODE>")])
(define_expand "add<mode>3"
[(set (match_operand:GPR 0 "register_operand")
*************** (define_insn_and_split "*addsi3_extended
*** 774,805 ****
;; ....................
;;
! (define_insn "subdf3"
! [(set (match_operand:DF 0 "register_operand" "=f")
! (minus:DF (match_operand:DF 1 "register_operand" "f")
! (match_operand:DF 2 "register_operand" "f")))]
! "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
! "sub.d\t%0,%1,%2"
! [(set_attr "type" "fadd")
! (set_attr "mode" "DF")])
!
! (define_insn "subsf3"
! [(set (match_operand:SF 0 "register_operand" "=f")
! (minus:SF (match_operand:SF 1 "register_operand" "f")
! (match_operand:SF 2 "register_operand" "f")))]
! "TARGET_HARD_FLOAT"
! "sub.s\t%0,%1,%2"
! [(set_attr "type" "fadd")
! (set_attr "mode" "SF")])
!
! (define_insn "subv2sf3"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (minus:V2SF (match_operand:V2SF 1 "register_operand" "f")
! (match_operand:V2SF 2 "register_operand" "f")))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "sub.ps\t%0,%1,%2"
[(set_attr "type" "fadd")
! (set_attr "mode" "SF")])
(define_insn "sub<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d")
--- 777,790 ----
;; ....................
;;
! (define_insn "sub<mode>3"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
! (match_operand:ANYF 2 "register_operand" "f")))]
! ""
! "sub.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
! (set_attr "mode" "<UNITMODE>")])
(define_insn "sub<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d")
*************** (define_insn "*subsi3_extended"
*** 828,890 ****
;; ....................
;;
! (define_expand "muldf3"
! [(set (match_operand:DF 0 "register_operand")
! (mult:DF (match_operand:DF 1 "register_operand")
! (match_operand:DF 2 "register_operand")))]
! "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"")
! (define_insn "muldf3_internal"
! [(set (match_operand:DF 0 "register_operand" "=f")
! (mult:DF (match_operand:DF 1 "register_operand" "f")
! (match_operand:DF 2 "register_operand" "f")))]
! "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_4300_MUL_FIX"
! "mul.d\t%0,%1,%2"
! [(set_attr "type" "fmul")
! (set_attr "mode" "DF")])
;; Early VR4300 silicon has a CPU bug where multiplies with certain
;; operands may corrupt immediately following multiplies. This is a
;; simple fix to insert NOPs.
! (define_insn "muldf3_r4300"
! [(set (match_operand:DF 0 "register_operand" "=f")
! (mult:DF (match_operand:DF 1 "register_operand" "f")
! (match_operand:DF 2 "register_operand" "f")))]
! "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_4300_MUL_FIX"
! "mul.d\t%0,%1,%2\;nop"
! [(set_attr "type" "fmul")
! (set_attr "mode" "DF")
! (set_attr "length" "8")])
!
! (define_expand "mulsf3"
! [(set (match_operand:SF 0 "register_operand")
! (mult:SF (match_operand:SF 1 "register_operand")
! (match_operand:SF 2 "register_operand")))]
! "TARGET_HARD_FLOAT"
! "")
!
! (define_insn "mulsf3_internal"
! [(set (match_operand:SF 0 "register_operand" "=f")
! (mult:SF (match_operand:SF 1 "register_operand" "f")
! (match_operand:SF 2 "register_operand" "f")))]
! "TARGET_HARD_FLOAT && !TARGET_4300_MUL_FIX"
! "mul.s\t%0,%1,%2"
! [(set_attr "type" "fmul")
! (set_attr "mode" "SF")])
!
! ;; See muldf3_r4300.
!
! (define_insn "mulsf3_r4300"
! [(set (match_operand:SF 0 "register_operand" "=f")
! (mult:SF (match_operand:SF 1 "register_operand" "f")
! (match_operand:SF 2 "register_operand" "f")))]
! "TARGET_HARD_FLOAT && TARGET_4300_MUL_FIX"
! "mul.s\t%0,%1,%2\;nop"
! [(set_attr "type" "fmul")
! (set_attr "mode" "SF")
! (set_attr "length" "8")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=f")
--- 813,847 ----
;; ....................
;;
! (define_expand "mul<mode>3"
! [(set (match_operand:SCALARF 0 "register_operand")
! (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
! (match_operand:SCALARF 2 "register_operand")))]
! ""
"")
! (define_insn "*mul<mode>3"
! [(set (match_operand:SCALARF 0 "register_operand" "=f")
! (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
! (match_operand:SCALARF 2 "register_operand" "f")))]
! "!TARGET_4300_MUL_FIX"
! "mul.<fmt>\t%0,%1,%2"
! [(set_attr "type" "fmul")
! (set_attr "mode" "<MODE>")])
;; Early VR4300 silicon has a CPU bug where multiplies with certain
;; operands may corrupt immediately following multiplies. This is a
;; simple fix to insert NOPs.
! (define_insn "*mul<mode>3_r4300"
! [(set (match_operand:SCALARF 0 "register_operand" "=f")
! (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
! (match_operand:SCALARF 2 "register_operand" "f")))]
! "TARGET_4300_MUL_FIX"
! "mul.<fmt>\t%0,%1,%2\;nop"
! [(set_attr "type" "fmul")
! (set_attr "mode" "<MODE>")
! (set_attr "length" "8")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=f")
*************** (define_insn "*<su>mul_acc_di"
*** 1672,1868 ****
;; Floating point multiply accumulate instructions.
! (define_insn ""
! [(set (match_operand:DF 0 "register_operand" "=f")
! (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
! (match_operand:DF 2 "register_operand" "f"))
! (match_operand:DF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
! "madd.d\t%0,%3,%1,%2"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "DF")])
!
! (define_insn ""
! [(set (match_operand:SF 0 "register_operand" "=f")
! (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
! (match_operand:SF 2 "register_operand" "f"))
! (match_operand:SF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
! "madd.s\t%0,%3,%1,%2"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
!
! (define_insn ""
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (plus:V2SF (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
! (match_operand:V2SF 2 "register_operand" "f"))
! (match_operand:V2SF 3 "register_operand" "f")))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "madd.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
!
! (define_insn ""
! [(set (match_operand:DF 0 "register_operand" "=f")
! (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
! (match_operand:DF 2 "register_operand" "f"))
! (match_operand:DF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
! "msub.d\t%0,%3,%1,%2"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "DF")])
! (define_insn ""
! [(set (match_operand:SF 0 "register_operand" "=f")
! (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
! (match_operand:SF 2 "register_operand" "f"))
! (match_operand:SF 3 "register_operand" "f")))]
!
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
! "msub.s\t%0,%3,%1,%2"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
!
! (define_insn ""
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (minus:V2SF (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
! (match_operand:V2SF 2 "register_operand" "f"))
! (match_operand:V2SF 3 "register_operand" "f")))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "msub.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
! (define_insn ""
! [(set (match_operand:DF 0 "register_operand" "=f")
! (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
! (match_operand:DF 2 "register_operand" "f"))
! (match_operand:DF 3 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
! && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (DFmode)"
! "nmadd.d\t%0,%3,%1,%2"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "DF")])
!
! (define_insn ""
! [(set (match_operand:DF 0 "register_operand" "=f")
! (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
! (match_operand:DF 2 "register_operand" "f"))
! (match_operand:DF 3 "register_operand" "f")))]
! "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
! && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (DFmode)"
! "nmadd.d\t%0,%3,%1,%2"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "DF")])
!
! (define_insn ""
! [(set (match_operand:SF 0 "register_operand" "=f")
! (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
! (match_operand:SF 2 "register_operand" "f"))
! (match_operand:SF 3 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
! && HONOR_SIGNED_ZEROS (SFmode)"
! "nmadd.s\t%0,%3,%1,%2"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
!
! (define_insn ""
! [(set (match_operand:SF 0 "register_operand" "=f")
! (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
! (match_operand:SF 2 "register_operand" "f"))
! (match_operand:SF 3 "register_operand" "f")))]
! "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
! && !HONOR_SIGNED_ZEROS (SFmode)"
! "nmadd.s\t%0,%3,%1,%2"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
!
! (define_insn "*nmaddv2sf"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (neg:V2SF (plus:V2SF (mult:V2SF
! (match_operand:V2SF 1 "register_operand" "f")
! (match_operand:V2SF 2 "register_operand" "f"))
! (match_operand:V2SF 3 "register_operand" "f"))))]
! "TARGET_PAIRED_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (V2SFmode)"
! "nmadd.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
! (define_insn "*nmaddv2sf_fastmath"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (minus:V2SF (mult:V2SF (neg:V2SF
! (match_operand:V2SF 1 "register_operand" "f"))
! (match_operand:V2SF 2 "register_operand" "f"))
! (match_operand:V2SF 3 "register_operand" "f")))]
! "TARGET_PAIRED_SINGLE_FLOAT && !HONOR_SIGNED_ZEROS (V2SFmode)"
! "nmadd.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
!
! (define_insn ""
! [(set (match_operand:DF 0 "register_operand" "=f")
! (neg:DF (minus:DF (mult:DF (match_operand:DF 2 "register_operand" "f")
! (match_operand:DF 3 "register_operand" "f"))
! (match_operand:DF 1 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
! && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (DFmode)"
! "nmsub.d\t%0,%1,%2,%3"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "DF")])
!
! (define_insn ""
! [(set (match_operand:DF 0 "register_operand" "=f")
! (minus:DF (match_operand:DF 1 "register_operand" "f")
! (mult:DF (match_operand:DF 2 "register_operand" "f")
! (match_operand:DF 3 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
! && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (DFmode)"
! "nmsub.d\t%0,%1,%2,%3"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "DF")])
!
! (define_insn ""
! [(set (match_operand:SF 0 "register_operand" "=f")
! (neg:SF (minus:SF (mult:SF (match_operand:SF 2 "register_operand" "f")
! (match_operand:SF 3 "register_operand" "f"))
! (match_operand:SF 1 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
! && HONOR_SIGNED_ZEROS (SFmode)"
! "nmsub.s\t%0,%1,%2,%3"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
!
! (define_insn ""
! [(set (match_operand:SF 0 "register_operand" "=f")
! (minus:SF (match_operand:SF 1 "register_operand" "f")
! (mult:SF (match_operand:SF 2 "register_operand" "f")
! (match_operand:SF 3 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
! && !HONOR_SIGNED_ZEROS (SFmode)"
! "nmsub.s\t%0,%1,%2,%3"
! [(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
! (define_insn "*nmsubv2sf"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (neg:V2SF (minus:V2SF
! (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
! (match_operand:V2SF 2 "register_operand" "f"))
! (match_operand:V2SF 3 "register_operand" "f"))))]
! "TARGET_PAIRED_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (V2SFmode)"
! "nmsub.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
! (define_insn "*nmsubv2sf_fastmath"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (minus:V2SF (match_operand:V2SF 1 "register_operand" "f")
! (mult:V2SF (match_operand:V2SF 2 "register_operand" "f")
! (match_operand:V2SF 3 "register_operand" "f"))))]
! "TARGET_PAIRED_SINGLE_FLOAT && !HONOR_SIGNED_ZEROS (V2SFmode)"
! "nmsub.ps\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
! (set_attr "mode" "SF")])
;;
;; ....................
--- 1629,1701 ----
;; Floating point multiply accumulate instructions.
! (define_insn "*madd<mode>"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
! (match_operand:ANYF 2 "register_operand" "f"))
! (match_operand:ANYF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_FUSED_MADD"
! "madd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "<UNITMODE>")])
! (define_insn "*msub<mode>"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
! (match_operand:ANYF 2 "register_operand" "f"))
! (match_operand:ANYF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_FUSED_MADD"
! "msub.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "<UNITMODE>")])
! (define_insn "*nmadd<mode>"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (neg:ANYF (plus:ANYF
! (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
! (match_operand:ANYF 2 "register_operand" "f"))
! (match_operand:ANYF 3 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
! && HONOR_SIGNED_ZEROS (<MODE>mode)"
! "nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "<UNITMODE>")])
! (define_insn "*nmadd<mode>_fastmath"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (minus:ANYF
! (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
! (match_operand:ANYF 2 "register_operand" "f"))
! (match_operand:ANYF 3 "register_operand" "f")))]
! "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
! && !HONOR_SIGNED_ZEROS (<MODE>mode)"
! "nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
! (set_attr "mode" "<UNITMODE>")])
! (define_insn "*nmsub<mode>"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (neg:ANYF (minus:ANYF
! (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
! (match_operand:ANYF 3 "register_operand" "f"))
! (match_operand:ANYF 1 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
! && HONOR_SIGNED_ZEROS (<MODE>mode)"
! "nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
! (set_attr "mode" "<UNITMODE>")])
! (define_insn "*nmsub<mode>_fastmath"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (minus:ANYF
! (match_operand:ANYF 1 "register_operand" "f")
! (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
! (match_operand:ANYF 3 "register_operand" "f"))))]
! "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
! && !HONOR_SIGNED_ZEROS (<MODE>mode)"
! "nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
! (set_attr "mode" "<UNITMODE>")])
;;
;; ....................
*************** (define_insn "abs<mode>2"
*** 2171,2199 ****
(set_attr "mode" "<MODE>")
(set_attr "length" "12")])
! (define_insn "absdf2"
! [(set (match_operand:DF 0 "register_operand" "=f")
! (abs:DF (match_operand:DF 1 "register_operand" "f")))]
! "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
! "abs.d\t%0,%1"
! [(set_attr "type" "fabs")
! (set_attr "mode" "DF")])
!
! (define_insn "abssf2"
! [(set (match_operand:SF 0 "register_operand" "=f")
! (abs:SF (match_operand:SF 1 "register_operand" "f")))]
! "TARGET_HARD_FLOAT"
! "abs.s\t%0,%1"
! [(set_attr "type" "fabs")
! (set_attr "mode" "SF")])
!
! (define_insn "absv2sf2"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (abs:V2SF (match_operand:V2SF 1 "register_operand" "f")))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "abs.ps\t%0,%1"
[(set_attr "type" "fabs")
! (set_attr "mode" "SF")])
;;
;; ....................
--- 2004,2016 ----
(set_attr "mode" "<MODE>")
(set_attr "length" "12")])
! (define_insn "abs<mode>2"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
! ""
! "abs.<fmt>\t%0,%1"
[(set_attr "type" "fabs")
! (set_attr "mode" "<UNITMODE>")])
;;
;; ....................
*************** (define_insn "negdi2"
*** 2278,2306 ****
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
! (define_insn "negdf2"
! [(set (match_operand:DF 0 "register_operand" "=f")
! (neg:DF (match_operand:DF 1 "register_operand" "f")))]
! "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
! "neg.d\t%0,%1"
! [(set_attr "type" "fneg")
! (set_attr "mode" "DF")])
!
! (define_insn "negsf2"
! [(set (match_operand:SF 0 "register_operand" "=f")
! (neg:SF (match_operand:SF 1 "register_operand" "f")))]
! "TARGET_HARD_FLOAT"
! "neg.s\t%0,%1"
! [(set_attr "type" "fneg")
! (set_attr "mode" "SF")])
!
! (define_insn "negv2sf2"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (neg:V2SF (match_operand:V2SF 1 "register_operand" "f")))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "neg.ps\t%0,%1"
[(set_attr "type" "fneg")
! (set_attr "mode" "SF")])
(define_insn "one_cmpl<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
--- 2095,2107 ----
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
! (define_insn "neg<mode>2"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
! ""
! "neg.<fmt>\t%0,%1"
[(set_attr "type" "fneg")
! (set_attr "mode" "<UNITMODE>")])
(define_insn "one_cmpl<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
*************** (define_expand "reload_outcc"
*** 3900,3980 ****
;; these instructions can only be used to load and store floating
;; point registers, that would probably cause trouble in reload.
! (define_insn "*lwxc1_<mode>"
! [(set (match_operand:SF 0 "register_operand" "=f")
! (mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
! (match_operand:P 2 "register_operand" "d"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
! "lwxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
! (set_attr "mode" "SF")])
! (define_insn "*ldxc1_<mode>"
! [(set (match_operand:DF 0 "register_operand" "=f")
! (mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
! (match_operand:P 2 "register_operand" "d"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
! "ldxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxload")
! (set_attr "mode" "DF")])
!
! (define_insn "*ldxc1_v2sf_si"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (mem:V2SF (plus:SI (match_operand:SI 1 "register_operand" "d")
! (match_operand:SI 2 "register_operand" "d"))))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "ldxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxload")
! (set_attr "mode" "SF")
! (set_attr "length" "4")])
!
! (define_insn "*ldxc1_v2sf_di"
! [(set (match_operand:V2SF 0 "register_operand" "=f")
! (mem:V2SF (plus:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:DI 2 "register_operand" "d"))))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "ldxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxload")
! (set_attr "mode" "SF")
! (set_attr "length" "4")])
!
! (define_insn "*swxc1_<mode>"
! [(set (mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
! (match_operand:P 2 "register_operand" "d")))
! (match_operand:SF 0 "register_operand" "f"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
! "swxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxstore")
! (set_attr "mode" "SF")])
!
! (define_insn "*sdxc1_<mode>"
! [(set (mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
! (match_operand:P 2 "register_operand" "d")))
! (match_operand:DF 0 "register_operand" "f"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
! "sdxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
! (set_attr "mode" "DF")])
!
! (define_insn "*sdxc1_v2sf_si"
! [(set (mem:V2SF (plus:SI (match_operand:SI 1 "register_operand" "d")
! (match_operand:SI 2 "register_operand" "d")))
! (match_operand:V2SF 0 "register_operand" "f"))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "sdxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxstore")
! (set_attr "mode" "SF")
! (set_attr "length" "4")])
!
! (define_insn "*sdxc1_v2sf_di"
! [(set (mem:V2SF (plus:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:DI 2 "register_operand" "d")))
! (match_operand:V2SF 0 "register_operand" "f"))]
! "TARGET_PAIRED_SINGLE_FLOAT"
! "sdxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxstore")
! (set_attr "mode" "SF")
! (set_attr "length" "4")])
;; 16-bit Integer moves
--- 3701,3723 ----
;; these instructions can only be used to load and store floating
;; point registers, that would probably cause trouble in reload.
! (define_insn "*<ANYF:loadx>_<P:mode>"
! [(set (match_operand:ANYF 0 "register_operand" "=f")
! (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
! (match_operand:P 2 "register_operand" "d"))))]
! "ISA_HAS_FP4"
! "<ANYF:loadx>\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
! (set_attr "mode" "<ANYF:UNITMODE>")])
! (define_insn "*<ANYF:storex>_<P:mode>"
! [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
! (match_operand:P 2 "register_operand" "d")))
! (match_operand:ANYF 0 "register_operand" "f"))]
! "ISA_HAS_FP4"
! "<ANYF:storex>\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
! (set_attr "mode" "<ANYF:UNITMODE>")])
;; 16-bit Integer moves
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