[committed] Change interpretation of MIPS CCV2 and CCV4
Richard Sandiford
rsandifo@redhat.com
Sun Aug 29 11:55:00 GMT 2004
Another thing I became increasingly uneasy about was:
/* We fake the value of CCV2 to be
0, if ANY is true <--> NOT 0, if ALL is false
1, if UPPER is true <--> NOT 1, if UPPER is false
2, if LOWER is true <--> NOT 2, if LOWER is false
3, if ALL is true <--> NOT 3, if ANY is false
and the implication that (reg:CCV2 x) can be simultaneously equal
to 0, 1 and 2. I realise that the middle-end doesn't generally try
to interpret CCmode values, so this probably doesn't cause problems
in practice. It does seem a little dangerous though.
The patch below changes the interpretation of CCV2 and CCV4 so that
they are 0 if "ALL are false" and -1 if "ALL are true". I chose -1
for the latter so that any subreg of CCV2 or CCV4 would also be
nonzero (i.e. true).
There's no need for special UPPER and LOWER values; we can just take
the appropriate CCmode subreg. This also allows us to get rid of the
special upper/lower branch patterns.
In turn, getting rid of the branch patterns allows us to get rid of
the new %Y and %y operand specifiers. The only other user was the
movtf_ps pattern, which had %y, but it can just as easily use %Q
instead. This also makes it more consistent with the patterns
that set the register; they also use %Q.
As before, I compared the output of MIPS's testsuite before and after
the patch (both big & little endian; forgot to mention that before).
There are no functional changes, but lower/upper branches against
$fcc0 are now written:
bc1t label
rather than:
bc1t $fcc0,label
because that's what the generic branch handling does. It should probably
always print the CC register if ISA_HAS_8CC, but that's for another day...
Applied to mainline.
Richard
* config/mips/mips.c (print_operand): Remove '%Y' and '%y'.
(mips_expand_4s_compare_builtin): Redefine CCV4 to be 0 if all
registers are false and -1 if all registers are true.
(mips_expand_ps_compare_builtin): Likewise CCV2. Use subregs for
MIPS_CMP_UPPER and MIPS_CMP_LOWER.
* config/mips/mips.md (mips_cond_move_tf_ps): Use %Q rather than %y.
(bc1any4t, bc1any4f): Adjust for new CCV4 interpretation.
(bc1any2t, bc1any2f): Likewise CCV2.
(bc1upper2t, bc1lower2t, bc1upper2f, bc1lower2f): Delete.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.458
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.458 mips.c
--- config/mips/mips.c 29 Aug 2004 10:01:25 -0000 1.458
+++ config/mips/mips.c 29 Aug 2004 10:25:15 -0000
@@ -4570,9 +4570,6 @@ print_fcc_operand (FILE *file, rtx op, e
't' like 'T', but with the EQ/NE cases reversed
'Z' print register and a comma, but print nothing for $fcc0
'R' print the reloc associated with LO_SUM
- 'Y' Check if the fcc register number is even. Then print the fcc register
- plus 1.
- 'y' Check if the fcc register number is even. Then print the fcc register.
'V' Check if the fcc register number divided by 4 is zero. Then print
the fcc register plus 2.
'v' Check if the fcc register number divided by 4 is zero. Then print
@@ -4812,12 +4809,6 @@ print_operand (FILE *file, rtx op, int l
else if (letter == 'Z')
print_fcc_operand (file, op, code, 1, 0, 1);
- else if (letter == 'Y')
- print_fcc_operand (file, op, code, 2, 1, 0);
-
- else if (letter == 'y')
- print_fcc_operand (file, op, code, 2, 0, 0);
-
else if (letter == 'V')
print_fcc_operand (file, op, code, 4, 2, 0);
@@ -10690,8 +10681,6 @@ mips_expand_ps_cond_move_builtin (enum m
rtx temp_target;
rtx src1;
rtx src2;
- enum rtx_code test_code;
- int compare_value;
arg0 = TREE_VALUE (arglist);
arg1 = TREE_VALUE (TREE_CHAIN (arglist));
@@ -10741,8 +10730,6 @@ mips_expand_ps_cond_move_builtin (enum m
/* Copy op2 to target */
emit_insn (gen_rtx_SET (tmode, target, op2));
- test_code = EQ;
- compare_value = 0;
switch (cmp_choice)
{
case MIPS_CMP_MOVT:
@@ -10793,7 +10780,6 @@ mips_expand_4s_compare_builtin (enum mip
rtx label1;
rtx label2;
rtx if_then_else;
- enum rtx_code test_code;
int compare_value;
if (target == 0 || GET_MODE (target) != SImode)
@@ -10832,27 +10818,26 @@ mips_expand_4s_compare_builtin (enum mip
if (!pat)
return 0;
- /* We fake the value of CCV4 to be
- 0, if ANY is true <--> NOT 0, if ALL is false
- 1, if ALL is true <--> NOT 1, if ANY is false
+ /* We fake the value of CCV4 to be:
+ 0 if all registers are false.
+ -1 if all registers are true.
+ an indeterminate value otherse.
Thus, we can map "enum mips_cmp_choice" to RTL comparison operators:
- MIPS_CMP_ANY -> (EQ 0)
- MIPS_CMP_ALL -> (EQ 1)
+ MIPS_CMP_ANY -> (NE 0)
+ MIPS_CMP_ALL -> (EQ -1).
However, because MIPS doesn't have "branch_all" instructions,
- for MIPS_CMP_ALL, we will use (NE 1) and reverse the assignment of
+ for MIPS_CMP_ALL, we will use (NE -1) and reverse the assignment of
the target to 1 first and then 0. */
switch (cmp_choice)
{
case MIPS_CMP_ANY:
- test_code = EQ;
compare_value = 0;
break;
case MIPS_CMP_ALL:
- test_code = NE;
- compare_value = 1;
+ compare_value = -1;
break;
default:
@@ -10870,7 +10855,7 @@ mips_expand_4s_compare_builtin (enum mip
label2 = gen_label_rtx ();
if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode,
- gen_rtx_fmt_ee (test_code, CCV4mode, temp_target,
+ gen_rtx_fmt_ee (NE, CCV4mode, temp_target,
GEN_INT (compare_value)),
gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
@@ -10986,7 +10971,6 @@ mips_expand_ps_compare_builtin (enum mip
rtx label1;
rtx label2;
rtx if_then_else;
- enum rtx_code test_code;
int compare_value;
if (target == 0 || GET_MODE (target) != SImode)
@@ -11013,41 +10997,39 @@ mips_expand_ps_compare_builtin (enum mip
if (!pat)
return 0;
- /* We fake the value of CCV2 to be
- 0, if ANY is true <--> NOT 0, if ALL is false
- 1, if UPPER is true <--> NOT 1, if UPPER is false
- 2, if LOWER is true <--> NOT 2, if LOWER is false
- 3, if ALL is true <--> NOT 3, if ANY is false
+ /* We fake the value of CCV2 to be:
+ 0 if all registers are false.
+ -1 if all registers are true.
+ an indeterminate value otherse.
Thus, we can map "enum mips_cmp_choice" to RTL comparison operators:
- MIPS_CMP_ANY -> (EQ 0)
- MIPS_CMP_UPPER -> (EQ 1)
- MIPS_CMP_LOWER -> (EQ 2)
- MIPS_CMP_ALL -> (EQ 3)
+ MIPS_CMP_ANY -> (NE 0)
+ MIPS_CMP_ALL -> (EQ -1).
- However, because MIPS doesn't have "branch_all" instructions,
- for MIPS_CMP_ALL, we will use (NE 3) and reverse the assignment of
- the target to 1 fisrt and then 0. */
+ However, because MIPS doesn't have "branch_all" instructions,
+ for MIPS_CMP_ALL, we will use (NE -1) and reverse the assignment of
+ the target to 1 first and then 0.
+
+ We handle MIPS_CMP_LOWER and MIPS_CMP_UPPER by taking the appropriate
+ CCmode subreg and comparing against zero in the normal way. */
switch (cmp_choice)
{
case MIPS_CMP_ANY:
- test_code = EQ;
compare_value = 0;
break;
case MIPS_CMP_UPPER:
- test_code = EQ;
- compare_value = 1;
+ temp_target = simplify_gen_subreg (CCmode, temp_target, CCV2mode, 4);
+ compare_value = 0;
break;
case MIPS_CMP_LOWER:
- test_code = EQ;
- compare_value = 2;
+ temp_target = simplify_gen_subreg (CCmode, temp_target, CCV2mode, 0);
+ compare_value = 0;
break;
case MIPS_CMP_ALL:
- test_code = NE;
- compare_value = 3;
+ compare_value = -1;
break;
default:
@@ -11066,8 +11048,9 @@ mips_expand_ps_compare_builtin (enum mip
if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode,
- gen_rtx_fmt_ee (test_code, CCV2mode, temp_target,
- GEN_INT (compare_value)),
+ gen_rtx_fmt_ee (NE, GET_MODE (temp_target),
+ temp_target,
+ GEN_INT (compare_value)),
gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
Index: config/mips/mips-ps-3d.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips-ps-3d.md,v
retrieving revision 1.2
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.2 mips-ps-3d.md
--- config/mips/mips-ps-3d.md 29 Aug 2004 10:01:25 -0000 1.2
+++ config/mips/mips-ps-3d.md 29 Aug 2004 10:25:17 -0000
@@ -56,8 +56,8 @@ (define_insn "mips_cond_move_tf_ps"
UNSPEC_MOVE_TF_PS))]
"TARGET_PAIRED_SINGLE_FLOAT"
"@
- movt.ps\t%0,%1,%y3
- movf.ps\t%0,%2,%y3"
+ movt.ps\t%0,%1,%Q3
+ movf.ps\t%0,%2,%Q3"
[(set_attr "type" "condmove")
(set_attr "mode" "SF")])
@@ -1374,7 +1374,7 @@ (define_insn "mips_cabs_ngt_ps"
; Branch on Any of Four Floating Point Condition Codes True
(define_insn "bc1any4t"
[(set (pc)
- (if_then_else (eq:CCV4 (match_operand:CCV4 0 "register_operand" "z")
+ (if_then_else (ne:CCV4 (match_operand:CCV4 0 "register_operand" "z")
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
@@ -1387,7 +1387,7 @@ (define_insn "bc1any4t"
(define_insn "bc1any4f"
[(set (pc)
(if_then_else (ne:CCV4 (match_operand:CCV4 0 "register_operand" "z")
- (const_int 1))
+ (const_int -1))
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_MIPS3D"
@@ -1398,7 +1398,7 @@ (define_insn "bc1any4f"
; Branch on Any of Two Floating Point Condition Codes True
(define_insn "bc1any2t"
[(set (pc)
- (if_then_else (eq:CCV2 (match_operand:CCV2 0 "register_operand" "z")
+ (if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
@@ -1407,36 +1407,11 @@ (define_insn "bc1any2t"
[(set_attr "type" "branch")
(set_attr "mode" "none")])
-; Branch on Upper of Two Floating Point Condition Codes True
-(define_insn "bc1upper2t"
- [(set (pc)
- (if_then_else (eq:CCV2 (match_operand:CCV2 0 "register_operand" "z")
- (const_int 1))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "TARGET_PAIRED_SINGLE_FLOAT"
- "%*bc1t\t%Y0,%1%/"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-; Branch on Lower of Two Floating Point Condition Codes True
-(define_insn "bc1lower2t"
- [(set (pc)
- (if_then_else (eq:CCV2 (match_operand:CCV2 0 "register_operand" "z")
- (const_int 2))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "TARGET_PAIRED_SINGLE_FLOAT"
- "%*bc1t\t%y0,%1%/"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-
; Branch on Any of Two Floating Point Condition Codes False
(define_insn "bc1any2f"
[(set (pc)
(if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
- (const_int 3))
+ (const_int -1))
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_MIPS3D"
@@ -1444,30 +1419,6 @@ (define_insn "bc1any2f"
[(set_attr "type" "branch")
(set_attr "mode" "none")])
-; Branch on Upper of Two Floating Point Condition Codes False
-(define_insn "bc1upper2f"
- [(set (pc)
- (if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
- (const_int 1))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "TARGET_PAIRED_SINGLE_FLOAT"
- "%*bc1f\t%Y0,%1%/"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-; Branch on Lower of Two Floating Point Condition Codes False
-(define_insn "bc1lower2f"
- [(set (pc)
- (if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
- (const_int 2))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "TARGET_PAIRED_SINGLE_FLOAT"
- "%*bc1f\t%y0,%1%/"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
;----------------------------------------------------------------------------
; Floating Point Reduced Precision Reciprocal Square Root Instructions.
;----------------------------------------------------------------------------
More information about the Gcc-patches
mailing list