[committed] mips.md macroisation (19/n)

Richard Sandiford rsandifo@redhat.com
Wed Aug 25 20:47:00 GMT 2004


Part 19 of the mips.md macroisation process.  This patch just fixes
a thinko in the macroisation of the conditional move patterns.
I realised last night that I'd forgotten to qualify the use of
the <ccreg> mode attribute.

This didn't make any difference in practice because the :MOVECC macro
gets expanded first, and everything works out OK.  However, the md.texi
documentation says that :GPR should have been expanded first, not :MOVECC.
That's not happening here because I'd forgotten that htab_traverse doesn't
guarantee a particular ordering.

In hindsight, it would probably be better if read-rtl.c required the
MODE: prefix when a pattern uses more than one mode macro.  I'm still
thinking about the ins and outs of that.

Bootstrapped & regression tested on mips-sgi-irix6.5.  There should
be no behavioural change.  Applied to head.

Richard


	* config/mips/mips.md (reg): Renamed mode attribute from ccreg.
	(*mov*_on_*): Adjust accordingly.  Add an explicit MOVECC: prefix.

Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.289
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.289 mips.md
--- config/mips/mips.md	25 Aug 2004 19:18:22 -0000	1.289
+++ config/mips/mips.md	25 Aug 2004 19:20:58 -0000
@@ -310,9 +310,9 @@ (define_mode_attr store [(SI "sw") (DI "
 ;; field but the equivalent daddiu has only a 5-bit field.
 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
 
-;; In MOVECC templates, this attribute gives the constraint to use
-;; for the condition register.
-(define_mode_attr ccreg [(SI "d") (DI "d") (CC "z")])
+;; This attribute gives the best constraint to use for registers of
+;; a given mode.
+(define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
 
 ;; This code macro allows all branch instructions to be generated from
 ;; a single define_expand template.
@@ -5688,7 +5688,7 @@ (define_insn "*mov<GPR:mode>_on_<MOVECC:
   [(set (match_operand:GPR 0 "register_operand" "=d,d")
 	(if_then_else:GPR
 	 (match_operator:MOVECC 4 "equality_operator"
-		[(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
+		[(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
 		 (const_int 0)])
 	 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
 	 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
@@ -5703,7 +5703,7 @@ (define_insn "*movsf_on_<MOVECC:mode>"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(if_then_else:SF
 	 (match_operator:MOVECC 4 "equality_operator"
-		[(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
+		[(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
 		 (const_int 0)])
 	 (match_operand:SF 2 "register_operand" "f,0")
 	 (match_operand:SF 3 "register_operand" "0,f")))]
@@ -5718,7 +5718,7 @@ (define_insn "*movdf_on_<MOVECC:mode>"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(if_then_else:DF
 	 (match_operator:MOVECC 4 "equality_operator"
-		[(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
+		[(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
 		 (const_int 0)])
 	 (match_operand:DF 2 "register_operand" "f,0")
 	 (match_operand:DF 3 "register_operand" "0,f")))]



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