[committed] mips.md macroisation (17/n)
Richard Sandiford
rsandifo@redhat.com
Tue Aug 24 20:51:00 GMT 2004
Part 17 of the mips.md macroisation process (the last of today's batch).
This patch handles the conditional move instructions. It removes the
'%B/%T' and '%b/%t' distinction and instead makes %T and %t check the
mode of the operator. It also removes ISA_HAS_INT_CONDMOVE: let's cross
that bridge when something actually needs it.
I'll combine the SFmode and DFmode patterns later (when combining
other floating-point ops). There should be no behavioural changes.
Bootstrapped & regression tested on mips-sgi-irix6.5. Also compared
the before and after output of gcc.c-torture and gcc.dg for -O2 -mips64.
Applied to head.
Richard
* config/mips/mips.h (ISA_HAS_INT_CONDMOVE): Delete.
* config/mips/mips.c (print_operand): Fold %B/%b handling into %T/%t,
using the mode of the operand to decide between them.
* config/mips/mips.md (MOVECC): New mode macro.
(ccreg): New mode attribute.
(*mov{si,di,sf,df}_on_{cc,si,di}): Name formerly unnamed patterns.
Redefine using :GPR and :MOVECC. Use %T and %t for the condition.
(mov[sd]icc): Redefine using :GPR.
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.360
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.360 mips.h
*** config/mips/mips.h 23 Aug 2004 07:00:22 -0000 1.360
--- config/mips/mips.h 24 Aug 2004 20:25:35 -0000
*************** #define ISA_HAS_CONDMOVE ((ISA_MI
*** 824,832 ****
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
- /* ISA has just the integer condition move instructions (movn,movz) */
- #define ISA_HAS_INT_CONDMOVE 0
-
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (ISA_MIPS4 \
--- 824,829 ----
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.454
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.454 mips.c
*** config/mips/mips.c 24 Aug 2004 20:23:55 -0000 1.454
--- config/mips/mips.c 24 Aug 2004 20:25:45 -0000
*************** mips_debugger_offset (rtx addr, HOST_WID
*** 4480,4489 ****
'F' print part of opcode for a floating-point branch condition.
'N' print part of opcode for a branch condition, inverted.
'W' print part of opcode for a floating-point branch condition, inverted.
! 'B' print 'z' for EQ, 'n' for NE
! 'b' print 'n' for EQ, 'z' for NE
! 'T' print 'f' for EQ, 't' for NE
! 't' print 't' for EQ, 'f' for NE
'Z' print register and a comma, but print nothing for $fcc0
'R' print the reloc associated with LO_SUM
--- 4480,4488 ----
'F' print part of opcode for a floating-point branch condition.
'N' print part of opcode for a branch condition, inverted.
'W' print part of opcode for a floating-point branch condition, inverted.
! 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
! 'z' for (eq:?I ...), 'n' for (ne:?I ...).
! 't' like 'T', but with the EQ/NE cases reversed
'Z' print register and a comma, but print nothing for $fcc0
'R' print the reloc associated with LO_SUM
*************** print_operand (FILE *file, rtx op, int l
*** 4772,4785 ****
else if (letter == 'd' || letter == 'x' || letter == 'X')
output_operand_lossage ("invalid use of %%d, %%x, or %%X");
! else if (letter == 'B')
! fputs (code == EQ ? "z" : "n", file);
! else if (letter == 'b')
! fputs (code == EQ ? "n" : "z", file);
! else if (letter == 'T')
! fputs (code == EQ ? "f" : "t", file);
! else if (letter == 't')
! fputs (code == EQ ? "t" : "f", file);
else if (CONST_GP_P (op))
fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
--- 4771,4781 ----
else if (letter == 'd' || letter == 'x' || letter == 'X')
output_operand_lossage ("invalid use of %%d, %%x, or %%X");
! else if (letter == 'T' || letter == 't')
! {
! int truth = (code == NE) == (letter == 'T');
! fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
! }
else if (CONST_GP_P (op))
fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.287
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.287 mips.md
*** config/mips/mips.md 24 Aug 2004 20:23:57 -0000 1.287
--- config/mips/mips.md 24 Aug 2004 20:25:51 -0000
*************** (define_mode_macro GPR [SI (DI "TARGET_6
*** 293,298 ****
--- 293,302 ----
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+ ;; This mode macro allows :MOVECC to be used anywhere that a
+ ;; conditional-move-type condition is needed.
+ (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
+
;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr d [(SI "") (DI "d")])
*************** (define_mode_attr store [(SI "sw") (DI "
*** 306,311 ****
--- 310,319 ----
;; field but the equivalent daddiu has only a 5-bit field.
(define_mode_attr si8_di5 [(SI "8") (DI "5")])
+ ;; In MOVECC templates, this attribute gives the constraint to use
+ ;; for the condition register.
+ (define_mode_attr ccreg [(SI "d") (DI "d") (CC "z")])
+
;; This code macro allows all branch instructions to be generated from
;; a single define_expand template.
(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
*************** (define_insn "hazard_nop"
*** 6019,6225 ****
;; MIPS4 Conditional move instructions.
! (define_insn ""
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (if_then_else:SI
! (match_operator:SI 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
! (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
! (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
! "@
! mov%B4\t%0,%z2,%1
! mov%b4\t%0,%z3,%1"
! [(set_attr "type" "condmove")
! (set_attr "mode" "SI")])
!
! (define_insn ""
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (if_then_else:SI
! (match_operator:DI 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
! (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
! (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
! "@
! mov%B4\t%0,%z2,%1
! mov%b4\t%0,%z3,%1"
! [(set_attr "type" "condmove")
! (set_attr "mode" "SI")])
!
! (define_insn ""
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (if_then_else:SI
! (match_operator:CC 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
! (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
! (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
! "@
! mov%T3\t%0,%z1,%4
! mov%t3\t%0,%z2,%4"
! [(set_attr "type" "condmove")
! (set_attr "mode" "SI")])
!
! (define_insn ""
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (if_then_else:DI
! (match_operator:SI 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
! (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
! (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
! "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
! "@
! mov%B4\t%0,%z2,%1
! mov%b4\t%0,%z3,%1"
! [(set_attr "type" "condmove")
! (set_attr "mode" "DI")])
!
! (define_insn ""
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (if_then_else:DI
! (match_operator:DI 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
! (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
! (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
! "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
! "@
! mov%B4\t%0,%z2,%1
! mov%b4\t%0,%z3,%1"
! [(set_attr "type" "condmove")
! (set_attr "mode" "DI")])
!
! (define_insn ""
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (if_then_else:DI
! (match_operator:CC 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
! (match_operand:DI 1 "reg_or_0_operand" "dJ,0")
! (match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
! "@
! mov%T3\t%0,%z1,%4
! mov%t3\t%0,%z2,%4"
! [(set_attr "type" "condmove")
! (set_attr "mode" "DI")])
!
! (define_insn ""
! [(set (match_operand:SF 0 "register_operand" "=f,f")
! (if_then_else:SF
! (match_operator:SI 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
! (match_operand:SF 2 "register_operand" "f,0")
! (match_operand:SF 3 "register_operand" "0,f")))]
! "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
! mov%B4.s\t%0,%2,%1
! mov%b4.s\t%0,%3,%1"
[(set_attr "type" "condmove")
! (set_attr "mode" "SF")])
! (define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator:DI 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
! mov%B4.s\t%0,%2,%1
! mov%b4.s\t%0,%3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "SF")])
! (define_insn ""
! [(set (match_operand:SF 0 "register_operand" "=f,f")
! (if_then_else:SF
! (match_operator:CC 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
! (match_operand:SF 1 "register_operand" "f,0")
! (match_operand:SF 2 "register_operand" "0,f")))]
! "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
! "@
! mov%T3.s\t%0,%1,%4
! mov%t3.s\t%0,%2,%4"
! [(set_attr "type" "condmove")
! (set_attr "mode" "SF")])
!
! (define_insn ""
! [(set (match_operand:DF 0 "register_operand" "=f,f")
! (if_then_else:DF
! (match_operator:SI 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
! (match_operand:DF 2 "register_operand" "f,0")
! (match_operand:DF 3 "register_operand" "0,f")))]
! "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
! "@
! mov%B4.d\t%0,%2,%1
! mov%b4.d\t%0,%3,%1"
! [(set_attr "type" "condmove")
! (set_attr "mode" "DF")])
!
! (define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator:DI 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
! mov%B4.d\t%0,%2,%1
! mov%b4.d\t%0,%3,%1"
! [(set_attr "type" "condmove")
! (set_attr "mode" "DF")])
!
! (define_insn ""
! [(set (match_operand:DF 0 "register_operand" "=f,f")
! (if_then_else:DF
! (match_operator:CC 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
! (match_operand:DF 1 "register_operand" "f,0")
! (match_operand:DF 2 "register_operand" "0,f")))]
! "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
! "@
! mov%T3.d\t%0,%1,%4
! mov%t3.d\t%0,%2,%4"
[(set_attr "type" "condmove")
(set_attr "mode" "DF")])
;; These are the main define_expand's used to make conditional moves.
! (define_expand "movsicc"
! [(set (match_dup 4) (match_operand 1 "comparison_operator"))
! (set (match_operand:SI 0 "register_operand")
! (if_then_else:SI (match_dup 5)
! (match_operand:SI 2 "reg_or_0_operand")
! (match_operand:SI 3 "reg_or_0_operand")))]
! "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
! {
! gen_conditional_move (operands);
! DONE;
! })
!
! (define_expand "movdicc"
[(set (match_dup 4) (match_operand 1 "comparison_operator"))
! (set (match_operand:DI 0 "register_operand")
! (if_then_else:DI (match_dup 5)
! (match_operand:DI 2 "reg_or_0_operand")
! (match_operand:DI 3 "reg_or_0_operand")))]
! "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
{
gen_conditional_move (operands);
DONE;
--- 6027,6086 ----
;; MIPS4 Conditional move instructions.
! (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
! [(set (match_operand:GPR 0 "register_operand" "=d,d")
! (if_then_else:GPR
! (match_operator:MOVECC 4 "equality_operator"
! [(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
! (const_int 0)])
! (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
! (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE"
"@
! mov%T4\t%0,%z2,%1
! mov%t4\t%0,%z3,%1"
[(set_attr "type" "condmove")
! (set_attr "mode" "<GPR:MODE>")])
! (define_insn "*movsf_on_<MOVECC:mode>"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator:MOVECC 4 "equality_operator"
! [(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
! mov%T4.s\t%0,%2,%1
! mov%t4.s\t%0,%3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "SF")])
! (define_insn "*movdf_on_<MOVECC:mode>"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator:MOVECC 4 "equality_operator"
! [(match_operand:MOVECC 1 "register_operand" "<ccreg>,<ccreg>")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
! mov%T4.d\t%0,%2,%1
! mov%t4.d\t%0,%3,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "DF")])
;; These are the main define_expand's used to make conditional moves.
! (define_expand "mov<mode>cc"
[(set (match_dup 4) (match_operand 1 "comparison_operator"))
! (set (match_operand:GPR 0 "register_operand")
! (if_then_else:GPR (match_dup 5)
! (match_operand:GPR 2 "reg_or_0_operand")
! (match_operand:GPR 3 "reg_or_0_operand")))]
! "ISA_HAS_CONDMOVE"
{
gen_conditional_move (operands);
DONE;
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