[committed] mips.md macroisation (4/n)
Richard Sandiford
rsandifo@redhat.com
Mon Aug 23 08:10:00 GMT 2004
Part 4 of the mips.md macroisation process. This patch handles the
abs, ffs and clz patterns.
The abs case is an example of the kind of consistency improvement I'm
hoping for with these macros. In current sources, abssi3 will dutifully
avoid using branch likely instructions if !GENERATE_BRANCH_LIKELY, but
absdi3 has no such check. This doesn't lead to incorrect code since
all 64-bit archs do support branch-likely. However, we shouldn't be
generating them when the user has told us not to, or when targetting
an ISA that has deprecated them.
The patch also removes ISA_HAS_DCLZ_DCLO since it is equivalent to
ISA_HAS_CLZ_CLO && TARGET_64BIT.
Bootstrapped & regression tested on mips-sgi-irix6.5. Applied to head.
Richard
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.360
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.360 mips.h
--- config/mips/mips.h 23 Aug 2004 07:00:22 -0000 1.360
+++ config/mips/mips.h 23 Aug 2004 07:14:07 -0000
@@ -863,11 +863,6 @@ #define ISA_HAS_CLZ_CLO ((ISA_MI
|| ISA_MIPS64 \
) && !TARGET_MIPS16)
-/* ISA has double-word count leading zeroes/ones instruction (not
- implemented). */
-#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
- && !TARGET_MIPS16)
-
/* ISA has three operand multiply instructions that put
the high part in an accumulator: mulhi or mulhiu. */
#define ISA_HAS_MULHI (TARGET_MIPS5400 \
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.274
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.274 mips.md
--- config/mips/mips.md 23 Aug 2004 07:13:13 -0000 1.274
+++ config/mips/mips.md 23 Aug 2004 07:14:14 -0000
@@ -1986,48 +1986,19 @@ (define_insn ""
;; Do not use the integer abs macro instruction, since that signals an
;; exception on -2147483648 (sigh).
-(define_insn "abssi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (abs:SI (match_operand:SI 1 "register_operand" "d")))]
+(define_insn "abs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (abs:GPR (match_operand:GPR 1 "register_operand" "d")))]
"!TARGET_MIPS16"
{
- operands[2] = const0_rtx;
-
- if (REGNO (operands[0]) == REGNO (operands[1]))
- {
- if (GENERATE_BRANCHLIKELY)
- return "%(bltzl\t%1,1f\;subu\t%0,%z2,%0\n%~1:%)";
- else
- return "bgez\t%1,1f%#\;subu\t%0,%z2,%0\n%~1:";
- }
+ if (REGNO (operands[0]) == REGNO (operands[1]) && GENERATE_BRANCHLIKELY)
+ return "%(bltzl\t%1,1f\;<d>subu\t%0,%.,%0\n%~1:%)";
else
- return "%(bgez\t%1,1f\;move\t%0,%1\;subu\t%0,%z2,%0\n%~1:%)";
+ return "%(bgez\t%1,1f\;move\t%0,%1\;<d>subu\t%0,%.,%0\n%~1:%)";
}
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "12")])
-
-(define_insn "absdi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (abs:DI (match_operand:DI 1 "register_operand" "d")))]
- "TARGET_64BIT && !TARGET_MIPS16"
-{
- unsigned int regno1;
- operands[2] = const0_rtx;
-
- if (GET_CODE (operands[1]) == REG)
- regno1 = REGNO (operands[1]);
- else
- regno1 = REGNO (XEXP (operands[1], 0));
-
- if (REGNO (operands[0]) == regno1)
- return "%(bltzl\t%1,1f\;dsubu\t%0,%z2,%0\n%~1:%)";
- else
- return "%(bgez\t%1,1f\;move\t%0,%1\;dsubu\t%0,%z2,%0\n%~1:%)";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "12")])
+ [(set_attr "type" "multi")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "12")])
(define_insn "absdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -2053,11 +2024,11 @@ (define_insn "abssf2"
;; ....................
;;
-(define_insn "ffssi2"
- [(set (match_operand:SI 0 "register_operand" "=&d")
- (ffs:SI (match_operand:SI 1 "register_operand" "d")))
- (clobber (match_scratch:SI 2 "=&d"))
- (clobber (match_scratch:SI 3 "=&d"))]
+(define_insn "ffs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=&d")
+ (ffs:GPR (match_operand:GPR 1 "register_operand" "d")))
+ (clobber (match_scratch:GPR 2 "=&d"))
+ (clobber (match_scratch:GPR 3 "=&d"))]
"!TARGET_MIPS16"
{
if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
@@ -2065,40 +2036,9 @@ (define_insn "ffssi2"
move\t%0,%.\;\
beq\t%1,%.,2f\n\
%~1:\tand\t%2,%1,0x0001\;\
-addu\t%0,%0,1\;\
-beq\t%2,%.,1b\;\
-srl\t%1,%1,1\n\
-%~2:%)";
-
- return "%(\
-move\t%0,%.\;\
-move\t%3,%1\;\
-beq\t%3,%.,2f\n\
-%~1:\tand\t%2,%3,0x0001\;\
-addu\t%0,%0,1\;\
-beq\t%2,%.,1b\;\
-srl\t%3,%3,1\n\
-%~2:%)";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "28")])
-
-(define_insn "ffsdi2"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ffs:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (match_scratch:DI 2 "=&d"))
- (clobber (match_scratch:DI 3 "=&d"))]
- "TARGET_64BIT && !TARGET_MIPS16"
-{
- if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
- return "%(\
-move\t%0,%.\;\
-beq\t%1,%.,2f\n\
-%~1:\tand\t%2,%1,0x0001\;\
-daddu\t%0,%0,1\;\
+<d>addu\t%0,%0,1\;\
beq\t%2,%.,1b\;\
-dsrl\t%1,%1,1\n\
+<d>srl\t%1,%1,1\n\
%~2:%)";
return "%(\
@@ -2106,14 +2046,14 @@ move\t%0,%.\;\
move\t%3,%1\;\
beq\t%3,%.,2f\n\
%~1:\tand\t%2,%3,0x0001\;\
-daddu\t%0,%0,1\;\
+<d>addu\t%0,%0,1\;\
beq\t%2,%.,1b\;\
-dsrl\t%3,%3,1\n\
+<d>srl\t%3,%3,1\n\
%~2:%)";
}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "28")])
+ [(set_attr "type" "multi")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "28")])
;;
;; ...................
@@ -2123,21 +2063,13 @@ dsrl\t%3,%3,1\n\
;; ...................
;;
-(define_insn "clzsi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (clz:SI (match_operand:SI 1 "register_operand" "d")))]
+(define_insn "clz<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
"ISA_HAS_CLZ_CLO"
- "clz\t%0,%1"
+ "<d>clz\t%0,%1"
[(set_attr "type" "clz")
- (set_attr "mode" "SI")])
-
-(define_insn "clzdi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (clz:DI (match_operand:DI 1 "register_operand" "d")))]
- "ISA_HAS_DCLZ_DCLO"
- "dclz\t%0,%1"
- [(set_attr "type" "clz")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "<MODE>")])
;;
;; ....................
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