RFC: MIPS paired single vector support

[cgd@broadcom.com]

At Mon, 16 Aug 2004 17:31:30 +0100, Nigel Stephens wrote:
> I had been thinking that we could snarf some bits from EF_MIPS_MACH. A
> certain range of values was "reserved" by Cygnus. I know that
> Algorithmics/MIPS used a few too. But maybe when the value is outside
> of the "reserved" ranges it could be used to give us some extra ASE
> bits -
> that's on the (perhaps rather hopeful) assumption that in the
> MIPS32/MIPS64 world we're not going to see so many incompatible
> extensions to the instruction set.

I don't know that that's a good assumption.

CP2 is officially available for vendors to use for extension
instructions, right?

Given that, I'd expect that there will be a lot of incompatible
extensions in CP2 space...  (Well, for values of 'a lot' that one
might expect when it costs a huge wad of $$ to fab a chip.  8-)


> >Ideally, it would be possible to come up with something compatible
> >with what SGI has done, too.
> 
> What is that? Do you mean the .MIPS.options section? We could consider
> extending it with some new "ODK" tags to hold CPU type (PrID value?)
> and ASE information. That sort-of fits in with Daniel's suggestion too.

Well, I mean, in general, compatible with SGI's use of these fields.

(I don't know what SGI has done specifically w.r.t. tagging for
different CPU types, and at this point I don't have time to figure it
out.)



chris