MIPS patch, for non-canonical conditional move patterns
James E Wilson
wilson@specifixinc.com
Sun Aug 15 01:11:00 GMT 2004
The MIPS conditional move patterns are non-canonical. They are missing
modes for the comparisons. They use VOIDmode instead of the canonical
mode which for MIPS is always the mode of the first compare operand.
I noticed this while tracking down problems with my new vector float
patterns. If you put a breakpoint in noce_emit_cmove, you will see that
it first creates a canonical conditional move pattern which fails to be
recognized, and then it calls emit_conditional_move which calls the
mov*cc patterns in the mips.md file which generate the noncanonical
ones. Fixing mips to use canonical ones means ifcvt will do less work,
and hence be slightly faster.
Also, in general, it is better to use canonical patterns to get best
optimization, though I don't have any evidence that we are missing
optimizations because of this.
This is an optional patch. I don't care much whether it goes in. I
just figured I noticed the problem, so I may as well provide a patch for
it.
This was tested with a sb1-elf cross compiler build from a combined
tree, with C and C++ enabled, and a make check. There were no
regressions.
The included testcase triggers all 12 conditional move patterns in the
mipd.md file, and demonstrates that they all still work with the patch.
--
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com
-------------- next part --------------
2004-08-13 James E Wilson <wilson@specifixinc.com>
* config/mips/mips.c (gen_conditional_move): Use GET_MODE (op0) instead
of VOIDmode for comparison code mode.
* config/mips/mips.md: For conditional move patterns, use mode of
first compare operand for comparison mode, instead of VOIDmode.
Index: mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.442
diff -p -r1.442 mips.c
*** mips.c 1 Aug 2004 11:36:25 -0000 1.442
--- mips.c 14 Aug 2004 03:13:11 -0000
*************** gen_conditional_move (rtx *operands)
*** 2934,2940 ****
mips_emit_compare (&code, &op0, &op1, true);
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
! gen_rtx_fmt_ee (code, VOIDmode,
op0, op1),
operands[2], operands[3])));
}
--- 2934,2941 ----
mips_emit_compare (&code, &op0, &op1, true);
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
! gen_rtx_fmt_ee (code,
! GET_MODE (op0),
op0, op1),
operands[2], operands[3])));
}
Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.264
diff -p -r1.264 mips.md
*** mips.md 1 Aug 2004 11:30:39 -0000 1.264
--- mips.md 14 Aug 2004 03:13:13 -0000
*************** dsrl\t%3,%3,1\n\
*** 7265,7273 ****
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator 4 "equality_op"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
--- 7265,7273 ----
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator:SI 4 "equality_op"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
*************** dsrl\t%3,%3,1\n\
*** 7280,7288 ****
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator 4 "equality_op"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
--- 7280,7288 ----
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator:DI 4 "equality_op"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
*************** dsrl\t%3,%3,1\n\
*** 7295,7304 ****
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator 3 "equality_op" [(match_operand:CC 4
! "register_operand"
! "z,z")
! (const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
--- 7295,7305 ----
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator:CC 3 "equality_op"
! [(match_operand:CC 4
! "register_operand"
! "z,z")
! (const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7311,7319 ****
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator 4 "equality_op"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
--- 7312,7320 ----
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator:SI 4 "equality_op"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
*************** dsrl\t%3,%3,1\n\
*** 7326,7334 ****
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator 4 "equality_op"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
--- 7327,7335 ----
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator:DI 4 "equality_op"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
*************** dsrl\t%3,%3,1\n\
*** 7341,7350 ****
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator 3 "equality_op" [(match_operand:CC 4
! "register_operand"
! "z,z")
! (const_int 0)])
(match_operand:DI 1 "reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
--- 7342,7352 ----
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator:CC 3 "equality_op"
! [(match_operand:CC 4
! "register_operand"
! "z,z")
! (const_int 0)])
(match_operand:DI 1 "reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
*************** dsrl\t%3,%3,1\n\
*** 7357,7365 ****
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator 4 "equality_op"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
--- 7359,7367 ----
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator:SI 4 "equality_op"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7372,7380 ****
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator 4 "equality_op"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
--- 7374,7382 ----
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator:DI 4 "equality_op"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7387,7396 ****
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator 3 "equality_op" [(match_operand:CC 4
! "register_operand"
! "z,z")
! (const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
--- 7389,7399 ----
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator:CC 3 "equality_op"
! [(match_operand:CC 4
! "register_operand"
! "z,z")
! (const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7403,7411 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator 4 "equality_op"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
--- 7406,7414 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator:SI 4 "equality_op"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7418,7426 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator 4 "equality_op"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
--- 7421,7429 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator:DI 4 "equality_op"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7433,7442 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator 3 "equality_op" [(match_operand:CC 4
! "register_operand"
! "z,z")
! (const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
--- 7436,7446 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator:CC 3 "equality_op"
! [(match_operand:CC 4
! "register_operand"
! "z,z")
! (const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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