kill FIXUNS_TRUNC_LIKE_FIX_TRUNC on alpha
Richard Henderson
rth@twiddle.net
Sun Oct 19 11:59:00 GMT 2003
As discussed.
r~
* config/alpha/alpha.c (fix_operator): New.
(divmod_operator): Tidy.
(alpha_emit_xfloating_cvt): Handle UNSIGNED_FIX.
* config/alpha/alpha.h (FIXUNS_TRUNC_LIKE_FIX_TRUNC): Remove.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (fix_truncdfsi_ieee): Use match_operator.
(fix_truncdfsi_internal, fix_truncdfdi_ieee): Likewise.
(fix_truncsfsi_ieee, fix_truncsfsi_internal): Likewise.
(fix_truncsfdi_ieee): Likewise.
(fix_truncdfdi2, fix_truncsfdi2): Turn into define_expand.
(fixuns_truncdfdi2, fixuns_truncsfdi2, fixuns_trunctfdi2): New.
* config/alpha/alpha-protos.h: Update.
Index: alpha-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha-protos.h,v
retrieving revision 1.51
diff -c -p -d -r1.51 alpha-protos.h
*** alpha-protos.h 11 Oct 2003 16:54:16 -0000 1.51
--- alpha-protos.h 19 Oct 2003 11:04:06 -0000
*************** extern int alpha_swapped_comparison_oper
*** 75,80 ****
--- 75,81 ----
extern int signed_comparison_operator (rtx, enum machine_mode);
extern int alpha_fp_comparison_operator (rtx, enum machine_mode);
extern int divmod_operator (rtx, enum machine_mode);
+ extern int fix_operator (rtx, enum machine_mode);
extern int aligned_memory_operand (rtx, enum machine_mode);
extern int unaligned_memory_operand (rtx, enum machine_mode);
extern int reg_or_unaligned_mem_operand (rtx, enum machine_mode);
Index: alpha.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.c,v
retrieving revision 1.332
diff -c -p -d -r1.332 alpha.c
*** alpha.c 11 Oct 2003 16:54:16 -0000 1.332
--- alpha.c 19 Oct 2003 11:04:13 -0000
*************** alpha_fp_comparison_operator (rtx op, en
*** 1179,1194 ****
int
divmod_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
! switch (GET_CODE (op))
! {
! case DIV: case MOD: case UDIV: case UMOD:
! return 1;
! default:
! break;
! }
! return 0;
}
/* Return 1 if this memory address is a known aligned register plus
--- 1179,1197 ----
int
divmod_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
! enum rtx_code code = GET_CODE (op);
! return (code == DIV || code == MOD || code == UDIV || code == UMOD);
! }
! /* Return 1 if this is a float->int conversion operator. */
!
! int
! fix_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
! {
! enum rtx_code code = GET_CODE (op);
!
! return (code == FIX || code == UNSIGNED_FIX);
}
/* Return 1 if this memory address is a known aligned register plus
*************** alpha_emit_xfloating_compare (enum rtx_c
*** 3774,3784 ****
/* Emit an X_floating library function call for a conversion. */
void
! alpha_emit_xfloating_cvt (enum rtx_code code, rtx operands[])
{
int noperands = 1, mode;
rtx out_operands[2];
const char *func;
func = alpha_lookup_xfloating_lib_func (code);
--- 3777,3791 ----
/* Emit an X_floating library function call for a conversion. */
void
! alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
{
int noperands = 1, mode;
rtx out_operands[2];
const char *func;
+ enum rtx_code code = orig_code;
+
+ if (code == UNSIGNED_FIX)
+ code = FIX;
func = alpha_lookup_xfloating_lib_func (code);
*************** alpha_emit_xfloating_cvt (enum rtx_code
*** 3801,3807 ****
}
alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
! gen_rtx_fmt_e (code, GET_MODE (operands[0]),
operands[1]));
}
--- 3808,3815 ----
}
alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
! gen_rtx_fmt_e (orig_code,
! GET_MODE (operands[0]),
operands[1]));
}
Index: alpha.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.h,v
retrieving revision 1.207
diff -c -p -d -r1.207 alpha.h
*** alpha.h 11 Oct 2003 16:54:17 -0000 1.207
--- alpha.h 19 Oct 2003 11:04:14 -0000
*************** do { \
*** 1338,1351 ****
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
- /* This flag, if defined, says the same insns that convert to a signed fixnum
- also convert validly to an unsigned one.
-
- We actually lie a bit here as overflow conditions are different. But
- they aren't being checked anyway. */
-
- #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
/* Max number of bytes we can move to or from memory
in one reasonably fast instruction. */
--- 1338,1343 ----
*************** do { \
*** 1654,1659 ****
--- 1646,1652 ----
{"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
{"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
{"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
+ {"fix_operator", {FIX, UNSIGNED_FIX}}, \
{"const0_operand", {CONST_INT, CONST_DOUBLE, CONST_VECTOR}}, \
{"samegp_function_operand", {SYMBOL_REF}}, \
{"direct_call_operand", {SYMBOL_REF}}, \
Index: alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.213
diff -c -p -d -r1.213 alpha.md
*** alpha.md 27 Sep 2003 04:48:12 -0000 1.213
--- alpha.md 19 Oct 2003 11:04:20 -0000
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 2337,2349 ****
(define_insn_and_split "*fix_truncdfsi_ieee"
[(set (match_operand:SI 0 "memory_operand" "=m")
! (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"#"
"&& reload_completed"
! [(set (match_dup 2) (fix:DI (match_dup 1)))
(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 3))]
""
--- 2337,2351 ----
(define_insn_and_split "*fix_truncdfsi_ieee"
[(set (match_operand:SI 0 "memory_operand" "=m")
! (subreg:SI
! (match_operator:DI 4 "fix_operator"
! [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"#"
"&& reload_completed"
! [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 3))]
""
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 2352,2373 ****
(define_insn_and_split "*fix_truncdfsi_internal"
[(set (match_operand:SI 0 "memory_operand" "=m")
! (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"#"
"&& reload_completed"
! [(set (match_dup 2) (fix:DI (match_dup 1)))
! (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
! (set (match_dup 0) (match_dup 3))]
;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
! "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "*fix_truncdfdi_ieee"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
! (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
--- 2354,2378 ----
(define_insn_and_split "*fix_truncdfsi_internal"
[(set (match_operand:SI 0 "memory_operand" "=m")
! (subreg:SI
! (match_operator:DI 3 "fix_operator"
! [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"#"
"&& reload_completed"
! [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
! (set (match_dup 4) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
! (set (match_dup 0) (match_dup 4))]
;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
! "operands[4] = gen_rtx_REG (SImode, REGNO (operands[2]));"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "*fix_truncdfdi_ieee"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
! (match_operator:DI 2 "fix_operator"
! [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 2375,2383 ****
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
! (define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
! (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
--- 2380,2389 ----
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
! (define_insn "*fix_truncdfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
! (match_operator:DI 2 "fix_operator"
! [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
"TARGET_FP"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 2385,2402 ****
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
;; Likewise between SFmode and SImode.
(define_insn_and_split "*fix_truncsfsi_ieee"
[(set (match_operand:SI 0 "memory_operand" "=m")
! (subreg:SI (fix:DI (float_extend:DF
! (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"#"
"&& reload_completed"
! [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 3))]
""
--- 2391,2422 ----
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
+ (define_expand "fix_truncdfdi2"
+ [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
+ (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
+ "TARGET_FP"
+ "")
+
+ (define_expand "fixuns_truncdfdi2"
+ [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
+ (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
+ "TARGET_FP"
+ "")
+
;; Likewise between SFmode and SImode.
(define_insn_and_split "*fix_truncsfsi_ieee"
[(set (match_operand:SI 0 "memory_operand" "=m")
! (subreg:SI
! (match_operator:DI 4 "fix_operator"
! [(float_extend:DF
! (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"#"
"&& reload_completed"
! [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 3))]
""
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 2405,2428 ****
(define_insn_and_split "*fix_truncsfsi_internal"
[(set (match_operand:SI 0 "memory_operand" "=m")
! (subreg:SI (fix:DI (float_extend:DF
! (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"#"
"&& reload_completed"
! [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
! (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
! (set (match_dup 0) (match_dup 3))]
;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
! "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "*fix_truncsfdi_ieee"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
! (fix:DI (float_extend:DF
! (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
--- 2425,2450 ----
(define_insn_and_split "*fix_truncsfsi_internal"
[(set (match_operand:SI 0 "memory_operand" "=m")
! (subreg:SI
! (match_operator:DI 3 "fix_operator"
! [(float_extend:DF
! (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"#"
"&& reload_completed"
! [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
! (set (match_dup 4) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
! (set (match_dup 0) (match_dup 4))]
;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
! "operands[4] = gen_rtx_REG (SImode, REGNO (operands[2]));"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "*fix_truncsfdi_ieee"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
! (match_operator:DI 2 "fix_operator"
! [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 2430,2439 ****
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
! (define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
! (fix:DI (float_extend:DF
! (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
"TARGET_FP"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
--- 2452,2461 ----
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
! (define_insn "*fix_truncsfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
! (match_operator:DI 2 "fix_operator"
! [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
"TARGET_FP"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 2441,2451 ****
--- 2463,2492 ----
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
+ (define_expand "fix_truncsfdi2"
+ [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
+ (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
+ "TARGET_FP"
+ "")
+
+ (define_expand "fixuns_truncsfdi2"
+ [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
+ (unsigned_fix:DI
+ (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
+ "TARGET_FP"
+ "")
+
(define_expand "fix_trunctfdi2"
[(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FIX, operands); DONE;")
+
+ (define_expand "fixuns_trunctfdi2"
+ [(use (match_operand:DI 0 "register_operand" ""))
+ (use (match_operand:TF 1 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
(define_insn "*floatdisf_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
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