[PATCH] gcc-3.4/changes.html: Document the m68k-uclinux target and ColdFire enhancements

[Bernardo Innocenti]

On Sunday 12 October 2003 21:26, Gerald Pfeifer wrote:

> > +++ changes.html	12 Oct 2003 03:07:24 -0000
> > +    <li>Bernardo Innocenti (Develer S.r.l.) has contributed
> > +    the <code>m68k-uclinux</code> target, based on former work done
> > +    by Paul Dale (SnapGear Inc.).  Code generation for the
> > +    <code>ColdFire</code> processors family has been enhanced and
> > extended
 +    to support <code>MCF 53xx</code> and
> > <code>MCF 54xx</code> +    cores, integrating former work done by
> > Peter Barada (Motorola).</li>
>
> I would add "the" before "cores" and avoid the <code> for ColdFire and
> MCF 53xx and MCF 54xx.

Oops... done!

> Also I recommend to remove   between first and last names, as this
> may make automatic formatting relative tough in some situations.

Ok, I've left them in the company and processor names because breaking
them apart is awkward.

>
> > +    similar to the <code>arm-pe</code> target, but it defaults to using
> > the APCS32
> 
> Would you mind splitting this long line?

Done.


> And thanks for also taking care of the other small issues you fixed; just
> briefly mention them (in an abstract way) in the CVS log as well.

Done.


> Please apply you patch with these changes and post the updated version
> afterwards.

Here it is:

diff -u -3 -p -u -p -r1.55 changes.html
--- changes.html	9 Oct 2003 10:59:43 -0000	1.55
+++ changes.html	12 Oct 2003 21:00:42 -0000
@@ -119,10 +119,10 @@
 	<pre>
 	template <typename T> void C<T>::g ()
 	{
-	  this->m = 0;
-	  this->f ();
-	  this->n = 0
-	  this->g ();
+	  this->m = 0;
+	  this->f ();
+	  this->n = 0
+	  this->g ();
 	}</pre></li>
 
     <li>The "named return value" and "implicit typename"
@@ -285,9 +285,16 @@
 <h2>New Targets and Target Specific Improvements</h2>
 
   <ul>
+    <li>Bernardo Innocenti (Develer S.r.l.) has contributed
+    the <code>m68k-uclinux</code> target, based on former work done
+    by Paul Dale (SnapGear Inc.).  Code generation for the
+    <code>ColdFire</code> processors family has been enhanced and extended
+    to support the MCF 53xx and MCF 54xx cores, integrating
+    former work done by Peter Barada (Motorola).</li>
+
     <li>Support for the Mitsubishi V850E1 processor has been added.
     This is a variant of the V850E processor with some additional
-    debugging instructions.  </li>
+    debugging instructions.</li>
     
     <li>Nicolas Pitre has contributed his hand-coded floating-point support
     code for ARM.  It is both significantly smaller and faster than the 
@@ -301,8 +308,8 @@
     line switch.</li>
     
     <li>A new ARM target has been added: <code>arm-wince-pe</code>.  This is
-    similar to the arm-pe target, but it defaults to using the APCS32
-    ABI.</li>
+    similar to the <code>arm-pe</code> target, but it defaults to using the
+    APCS32 ABI.</li>
 
     <li>The existing ARM pipeline description has been converted to
     the use the <a
@@ -356,7 +363,7 @@
       <li>the first word of the structure would have been passed in
 	  a register.</li>
     </ul>
-    Note that only big-endian n32 & n64 targets (such as IRIX 6) are
+    Note that only big-endian n32 & n64 targets (such as IRIX 6) are
     affected.</li>
 
     <li>More processor configuration options for Xtensa processors are


-- 
  // Bernardo Innocenti - Develer S.r.l., R&D dept.
\X/  http://www.develer.com/

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