[patch] arch-status.html: New. (Take 4)

[Segher Boessenkool]

Kazu Hirata wrote:
> Hi Segher,
> 
> > > C       Architecture does not have a single condition code register.
> > 
> > > rs6000   | HMSLQNFI BD lqrc f m dha e
> > 
> > rs6000   | HMSLQNFICBD lqrc f m dha e
> > 
> > Seems like PowerPC only needs some work in the machine description <g>.
> 
> Is this because of the following from rs6000.h?
> 
> #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)

PowerPC has 8 four-bit condition registers (or, depending on your viewpoint,
32 one-bit ones); but it has only one carry bit (and only one overflow bit,
etc.)

The condition register (cr0..cr7) are all part of one big register (CR) but
they are separately usable (most importantly, by the compare and branch
conditional and move to/from CR instructions).  So, for all practical
purposes, PowerPC has 8 condition code registers.  They are not fully
orthogonal though: intructions that have the "record" bit set, will set
cr0, cr1, or cr6 depending on the result of the operation, for resp.
fixed-point, floating-point, or VMX instructions.  Also, in the ABIs some
cr's are volatile, while others are not.

Anyway, PowerPC has more than one set of condition codes :-)


Segher