Frame-related delay slot insns

[Richard Sandiford]

Richard Henderson <rth@redhat.com> writes:
> On Tue, May 06, 2003 at 04:23:24PM +0100, Richard Sandiford wrote:
> > With my patch we generated:
> > 
> >         ...some stuff...
> > LD1:
> > ...
> > LDn:
> > LB:
> >         B
> >         D1
> >         ...
> >         Dn
> > 
> > but it sounds from what you say like the PA needs:
> > 
> >         ...some stuff...
> > LB:
> > LD1:
> > ...
> > LDn:
> >         B
> >         D1
> >         ...
> >         Dn
> > 
> > instead.
> 
> Note that these are equivalent as far as unwind info is concerned,
> because all of the L labels are at the same address.

Even when there are dependencies between the insns?  I assumed the
effects would still be sequential, i.e. we'd do the equivalent of:

        advance to LB
        do EB
        advacne to LD1
        do ED1
        ...

(where the advances would presumably get optimised away).
But the mips case is so simple, it's not easy to test.

At first, I was worried about dependences between B and the
delay slot insns, but I realise now that reorg probably can't
handle such cases anyway.

Richard