[patch] h8300: Improve one-bit zero_extract.

[Kazu Hirata]

Hi,

Attached is a patch to improve one-bit zero_extract.

Currently, one-bit extraction is done like

 	bld	#6,r2l  ; load a bit to carry
	xor.l	er5,er5 ; clear the destination (4 bytes)
 	bst	#0,r5l  ; set the bit from carry

If we use sub.l, which destroys the carry flag, we can do this a
little shorter.

	sub.l	er5,er5 ; clear the destination (2 bytes)
 	bld	#6,r2l  ; load a bit
 	bst	#0,r5l  ; set the bit

Tested on h8300 port.  Committed.

Kazu Hirata

2003-03-05  Kazu Hirata  <kazu@cs.umass.edu>

	* config/h8300/h8300.c (output_simode_bld): Clear the
	destination first if possible.
	* config/h8300/h8300.md (extzv_1_r_h8300hs): Add an
	alternative.
	(extzv_1_r_inv_h8300hs): Likewise.

Index: h8300.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.c,v
retrieving revision 1.217
diff -c -r1.217 h8300.c
*** h8300.c	2 Mar 2003 19:12:44 -0000	1.217
--- h8300.c	5 Mar 2003 21:05:39 -0000
***************
*** 4112,4125 ****
      }
    else
      {
        /* Output the bit load or bit inverse load.  */
        if (bild)
  	output_asm_insn ("bild\t%Z2,%Y1", operands);
        else
  	output_asm_insn ("bld\t%Z2,%Y1", operands);
  
!       /* Clear the destination register and perform the bit store.  */
!       output_asm_insn ("xor.l\t%S0,%S0\n\tbst\t#0,%w0", operands);
      }
  
    /* All done.  */
--- 4112,4135 ----
      }
    else
      {
+       /* Determine if we can clear the destination first.  */
+       int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
+ 			 && REGNO (operands[0]) != REGNO (operands[1]));
+ 
+       if (clear_first)
+ 	output_asm_insn ("sub.l\t%S0,%S0", operands);
+ 
        /* Output the bit load or bit inverse load.  */
        if (bild)
  	output_asm_insn ("bild\t%Z2,%Y1", operands);
        else
  	output_asm_insn ("bld\t%Z2,%Y1", operands);
  
!       if (!clear_first)
! 	output_asm_insn ("xor.l\t%S0,%S0", operands);
! 
!       /* Perform the bit store.  */
!       output_asm_insn ("bst\t#0,%w0", operands);
      }
  
    /* All done.  */
Index: h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.186
diff -c -r1.186 h8300.md
*** h8300.md	4 Mar 2003 14:14:53 -0000	1.186
--- h8300.md	5 Mar 2003 21:05:40 -0000
***************
*** 2503,2517 ****
     (set_attr "length" "8")])
  
  (define_insn "*extzv_1_r_h8300hs"
!   [(set (match_operand:SI 0 "register_operand" "=r")
! 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
  			 (const_int 1)
! 			 (match_operand 2 "const_int_operand" "n")))]
    "(TARGET_H8300H || TARGET_H8300S)
     && INTVAL (operands[2]) < 16"
    "* return output_simode_bld (0, operands);"
!   [(set_attr "cc" "clobber")
!    (set_attr "length" "8")])
  
  ;;
  ;; Inverted loads with a 32bit destination.
--- 2503,2517 ----
     (set_attr "length" "8")])
  
  (define_insn "*extzv_1_r_h8300hs"
!   [(set (match_operand:SI 0 "register_operand" "=r,r")
! 	(zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
  			 (const_int 1)
! 			 (match_operand 2 "const_int_operand" "n,n")))]
    "(TARGET_H8300H || TARGET_H8300S)
     && INTVAL (operands[2]) < 16"
    "* return output_simode_bld (0, operands);"
!   [(set_attr "cc" "clobber,clobber")
!    (set_attr "length" "8,6")])
  
  ;;
  ;; Inverted loads with a 32bit destination.
***************
*** 2531,2547 ****
     (set_attr "length" "8")])
  
  (define_insn "*extzv_1_r_inv_h8300hs"
!   [(set (match_operand:SI 0 "register_operand" "=r")
! 	(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
! 				 (match_operand 3 "const_int_operand" "n"))
  			 (const_int 1)
! 			 (match_operand 2 "const_int_operand" "n")))]
    "(TARGET_H8300H || TARGET_H8300S)
     && INTVAL (operands[2]) < 16
     && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
    "* return output_simode_bld (1, operands);"
!   [(set_attr "cc" "clobber")
!    (set_attr "length" "8")])
  
  (define_expand "insv"
    [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
--- 2531,2547 ----
     (set_attr "length" "8")])
  
  (define_insn "*extzv_1_r_inv_h8300hs"
!   [(set (match_operand:SI 0 "register_operand" "=r,r")
! 	(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
! 				 (match_operand 3 "const_int_operand" "n,n"))
  			 (const_int 1)
! 			 (match_operand 2 "const_int_operand" "n,n")))]
    "(TARGET_H8300H || TARGET_H8300S)
     && INTVAL (operands[2]) < 16
     && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
    "* return output_simode_bld (1, operands);"
!   [(set_attr "cc" "clobber,clobber")
!    (set_attr "length" "8,6")])
  
  (define_expand "insv"
    [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")