PowerPC performance tuning

[David Edelsohn]

	Multipass DFA Lookahead does not help performance in my recent
tests, so I am disabling it on PowerPC.

	Also, until the heuristics are improved in the first scheduling
pass, performance generally improves by artificially limiting the issue
rate to 1.  Additionally, the RTL prior to register allocation contains a
lot of extraneous instructions and misses spilling and reload, so it does
not make to schedule those artificial instructions against the detailed
dispatch of the processor.

David


	* config/rs6000/rs6000.c (rs6000_multipass_dfa_lookahead): Delete.
	(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Delete.
	(rs6000_variable_issue): Do not return negative value.
	(rs6000_issue_rate): Uniformly set issue rate to 1 for first
	scheduling pass.

Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.427
diff -c -p -r1.427 rs6000.c
*** rs6000.c	25 Feb 2003 23:11:54 -0000	1.427
--- rs6000.c	3 Mar 2003 21:52:10 -0000
*************** static void rs6000_xcoff_encode_section_
*** 228,234 ****
       ATTRIBUTE_UNUSED;
  static bool rs6000_binds_local_p PARAMS ((tree));
  static int rs6000_use_dfa_pipeline_interface PARAMS ((void));
- static int rs6000_multipass_dfa_lookahead PARAMS ((void));
  static int rs6000_variable_issue PARAMS ((FILE *, int, rtx, int));
  static bool rs6000_rtx_costs PARAMS ((rtx, int, int, int *));
  static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int));
--- 228,233 ----
*************** static const char alt_reg_names[][8] =
*** 386,393 ****
  
  #undef  TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE 
  #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
- #undef  TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
- #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_multipass_dfa_lookahead
  #undef  TARGET_SCHED_VARIABLE_ISSUE
  #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
  
--- 385,390 ----
*************** rs6000_use_dfa_pipeline_interface ()
*** 12228,12242 ****
    return 1;
  }
  
- static int
- rs6000_multipass_dfa_lookahead ()
- {
-   if (rs6000_cpu == PROCESSOR_POWER4)
-     return 4;
-   else
-     return 1;
- }
- 
  /* Power4 load update and store update instructions are cracked into a
     load or store and an integer insn which are executed in the same cycle.
     Branches have their own dispatch slot which does not count against the
--- 12225,12230 ----
*************** rs6000_variable_issue (stream, verbose, 
*** 12264,12270 ****
        else if (type == TYPE_LOAD_U || type == TYPE_STORE_U
  	       || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
  	       || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR)
! 	return more - 2;
        else
  	return more - 1;
      }
--- 12252,12258 ----
        else if (type == TYPE_LOAD_U || type == TYPE_STORE_U
  	       || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
  	       || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR)
! 	return more > 2 ? more - 2 : 0;
        else
  	return more - 1;
      }
*************** rs6000_adjust_priority (insn, priority)
*** 12380,12385 ****
--- 12368,12377 ----
  static int
  rs6000_issue_rate ()
  {
+   /* Use issue rate of 1 for first scheduling pass to decrease degradation.  */
+   if (!reload_completed)
+     return 1;
+ 
    switch (rs6000_cpu_attr) {
    case CPU_RIOS1:  /* ? */
    case CPU_RS64A: