mips patch: remove workarounds for adding -32768
Richard Sandiford
rsandifo@redhat.com
Sat Jun 28 19:02:00 GMT 2003
The mips add expanders have code like:
/* The mips16 assembler handles -32768 correctly, and so does gas,
but some other MIPS assemblers think that -32768 needs to be
loaded into a register before it can be added in. */
if (! TARGET_MIPS16
&& ! TARGET_GAS
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == -32768)
operands[2] = force_reg (SImode, operands[2]);
I think this is a hangover from the days when (for whatever reason)
we used the subu and dsubu macros to add negative constants.
I tried running:
dsubu $4,$5,0x8000
through the irix assembler and it does indeed use a register temporary:
li $at,0x8000
dsubu $4,$5,$at
Nowadays we use the addiu and daddiu instructions explicitly so
I don't think there's any need for the workaround. The irix
assemblers seem to cope with:
daddiu $4,$5,-32768
and any assembler that didn't would be pretty broken...
Anyway, these workarounds can cause an ICE in certain conditions.
Rainer saw one such in an irix o32 bootstrap. The problem is that
the constant-splitting code in mips.c isn't aware of the -32768
restriction and so can generate unrecognisable insns. We either
need to add similar hacks there or remove the existing ones.
I notice that there's more suspicious-looking patterns in this area:
ones that match (sub foo (const_int X)) instead of (add foo (const -X)).
But they're used regardless of the TARGET_GAS setting and aren't directly
related to the current problem. I hope to look into it sometime soon.
In the meantime, this patch should at least be a step in the
right direction.
Tested on mips-sgi-irix6.5 with native tools, and on other
targets as usual. OK to install?
Richard
* config/mips/mips.md (addsi3): Remove workaround for adds of -32768.
(addsi3_internal, adddi3, adddi3_internal_2): Likewise.
(adddi3_internal_3, addsi3_internal_2): Likewise.
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.177
diff -c -d -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.177 mips.md
*** config/mips/mips.md 17 Jun 2003 20:50:41 -0000 1.177
--- config/mips/mips.md 26 Jun 2003 20:35:02 -0000
*************** (define_expand "addsi3"
*** 703,717 ****
""
"
{
- /* The mips16 assembler handles -32768 correctly, and so does gas,
- but some other MIPS assemblers think that -32768 needs to be
- loaded into a register before it can be added in. */
- if (! TARGET_MIPS16
- && ! TARGET_GAS
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == -32768)
- operands[2] = force_reg (SImode, operands[2]);
-
/* If a large stack adjustment was forced into a register, we may be
asked to generate rtx such as:
--- 703,708 ----
*************** (define_insn "addsi3_internal"
*** 738,747 ****
[(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:SI 2 "arith_operand" "d,Q")))]
! "! TARGET_MIPS16
! && (TARGET_GAS
! || GET_CODE (operands[2]) != CONST_INT
! || INTVAL (operands[2]) != -32768)"
"@
addu\\t%0,%z1,%2
addiu\\t%0,%z1,%2"
--- 729,735 ----
[(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:SI 2 "arith_operand" "d,Q")))]
! "!TARGET_MIPS16"
"@
addu\\t%0,%z1,%2
addiu\\t%0,%z1,%2"
*************** (define_expand "adddi3"
*** 888,902 ****
"TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
"
{
- /* The mips16 assembler handles -32768 correctly, and so does gas,
- but some other MIPS assemblers think that -32768 needs to be
- loaded into a register before it can be added in. */
- if (! TARGET_MIPS16
- && ! TARGET_GAS
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == -32768)
- operands[2] = force_reg (DImode, operands[2]);
-
/* If a large stack adjustment was forced into a register, we may be
asked to generate rtx such as:
--- 876,881 ----
*************** (define_insn "adddi3_internal_2"
*** 1010,1019 ****
(plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
(match_operand:DI 2 "small_int" "P,J,N")))
(clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
! "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
! && (TARGET_GAS
! || GET_CODE (operands[2]) != CONST_INT
! || INTVAL (operands[2]) != -32768)"
"@
addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
move\\t%L0,%L1\;move\\t%M0,%M1
--- 989,995 ----
(plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
(match_operand:DI 2 "small_int" "P,J,N")))
(clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
! "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
"@
addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
move\\t%L0,%L1\;move\\t%M0,%M1
*************** (define_insn "adddi3_internal_3"
*** 1074,1084 ****
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:DI 2 "arith_operand" "d,Q")))]
! "TARGET_64BIT
! && !TARGET_MIPS16
! && (TARGET_GAS
! || GET_CODE (operands[2]) != CONST_INT
! || INTVAL (operands[2]) != -32768)"
"@
daddu\\t%0,%z1,%2
daddiu\\t%0,%z1,%2"
--- 1050,1056 ----
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:DI 2 "arith_operand" "d,Q")))]
! "TARGET_64BIT && !TARGET_MIPS16"
"@
daddu\\t%0,%z1,%2
daddiu\\t%0,%z1,%2"
*************** (define_insn "addsi3_internal_2"
*** 1221,1231 ****
[(set (match_operand:DI 0 "register_operand" "=d,d")
(sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:SI 2 "arith_operand" "d,Q"))))]
! "TARGET_64BIT
! && !TARGET_MIPS16
! && (TARGET_GAS
! || GET_CODE (operands[2]) != CONST_INT
! || INTVAL (operands[2]) != -32768)"
"@
addu\\t%0,%z1,%2
addiu\\t%0,%z1,%2"
--- 1193,1199 ----
[(set (match_operand:DI 0 "register_operand" "=d,d")
(sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:SI 2 "arith_operand" "d,Q"))))]
! "TARGET_64BIT && !TARGET_MIPS16"
"@
addu\\t%0,%z1,%2
addiu\\t%0,%z1,%2"
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