applied to sh port: change complex alignments (changes abi), and assorted other bug fixes
Joern Rennecke
joern.rennecke@superh.com
Tue Jun 17 18:04:00 GMT 2003
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2003-06-17 J"orn Rennecke <joern.rennecke@superh.com>
* sh.h (ROUND_TYPE_ALIGN, LOCAL_ALIGNMENT): Complex modes
are aligned like integral modes.
(SH5_WOULD_BE_PARTIAL_NREGS): Also test for CDImode and DCmode.
* sh.h (EXTRA_CONSTRAINT_Csy): Allow PIC_DIRECT_ADDR_P.
(LEGITIMATE_PIC_OPERAND_P): Allow LABEL_REF.
* sh.md (*pt): Remove.
* sh.h (REG_ALLOC_ORDER): Avoid squandering call-saved registers.
* sh.md (return_media_rte): New pattern.
(return_media): Use it.
Index: config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.209
diff -p -r1.209 sh.h
*** config/sh/sh.h 17 Jun 2003 16:28:15 -0000 1.209
--- config/sh/sh.h 17 Jun 2003 16:28:55 -0000
*************** do { \
*** 619,624 ****
--- 619,641 ----
&& (ALIGN) < FASTEST_ALIGNMENT) \
? FASTEST_ALIGNMENT : (ALIGN))
+ /* get_mode_alignment assumes complex values are always held in multiple
+ registers, but that is not the case on the SH; CQImode and CHImode are
+ held in a single integer register. SH5 also holds CSImode and SCmode
+ values in integer regsters. Thus the alignment needs to be bumped up
+ to match the size of the mode. */
+ #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
+ (MAX ((GET_MODE_CLASS (TYPE_MODE (STRUCT)) == MODE_COMPLEX_INT \
+ || GET_MODE_CLASS (TYPE_MODE (STRUCT)) == MODE_COMPLEX_FLOAT) \
+ ? MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (STRUCT))) \
+ : (COMPUTED), \
+ (SPECIFIED)))
+ #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
+ ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
+ || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
+ ? MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
+ : ALIGN)
+
/* Make arrays of chars word-aligned for the same reasons. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE \
*************** extern int regno_reg_class[FIRST_PSEUDO_
*** 1264,1289 ****
and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
spilled or used otherwise, we better have the FP_REGS allocated first. */
#define REG_ALLOC_ORDER \
! { 65, 66, 67, 68, 69, 70, 71, 64, \
! 72, 73, 74, 75, 76, 77, 78, 79, \
! 136,137,138,139,140,141,142,143, \
! 80, 81, 82, 83, 84, 85, 86, 87, \
! 88, 89, 90, 91, 92, 93, 94, 95, \
! 96, 97, 98, 99,100,101,102,103, \
104,105,106,107,108,109,110,111, \
112,113,114,115,116,117,118,119, \
120,121,122,123,124,125,126,127, \
! 151, 1, 2, 3, 7, 6, 5, 4, \
! 0, 8, 9, 10, 11, 12, 13, 14, \
! 16, 17, 18, 19, 20, 21, 22, 23, \
! 24, 25, 26, 27, 28, 29, 30, 31, \
! 32, 33, 34, 35, 36, 37, 38, 39, \
! 40, 41, 42, 43, 44, 45, 46, 47, \
! 48, 49, 50, 51, 52, 53, 54, 55, \
! 56, 57, 58, 59, 60, 61, 62, 63, \
! 150, 15,145,146,147,144,148,149, \
128,129,130,131,132,133,134,135, \
! 152 }
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
--- 1281,1315 ----
and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
spilled or used otherwise, we better have the FP_REGS allocated first. */
#define REG_ALLOC_ORDER \
! {/* Caller-saved FPRs */ \
! 65, 66, 67, 68, 69, 70, 71, 64, \
! 72, 73, 74, 75, 80, 81, 82, 83, \
! 84, 85, 86, 87, 88, 89, 90, 91, \
! 92, 93, 94, 95, 96, 97, 98, 99, \
! /* Callee-saved FPRs */ \
! 76, 77, 78, 79,100,101,102,103, \
104,105,106,107,108,109,110,111, \
112,113,114,115,116,117,118,119, \
120,121,122,123,124,125,126,127, \
! 136,137,138,139,140,141,142,143, \
! /* FPSCR */ 151, \
! /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
! 1, 2, 3, 7, 6, 5, 4, 0, \
! 8, 9, 17, 19, 20, 21, 22, 23, \
! 36, 37, 38, 39, 40, 41, 42, 43, \
! 60, 61, 62, \
! /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
! 10, 11, 12, 13, 14, 18, \
! /* SH5 callee-saved GPRs */ \
! 28, 29, 30, 31, 32, 33, 34, 35, \
! 44, 45, 46, 47, 48, 49, 50, 51, \
! 52, 53, 54, 55, 56, 57, 58, 59, \
! /* FPUL */ 150, \
! /* SH5 branch target registers */ \
128,129,130,131,132,133,134,135, \
! /* Fixed registers */ \
! 15, 16, 24, 25, 26, 27, 63,144, \
! 145,146,147,148,149,152 }
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
*************** do { \
*** 2158,2164 ****
: 0)
#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
! (TARGET_SH5 && ((MODE) == BLKmode || (MODE) == TImode) \
&& ((CUM).arg_count[(int) SH_ARG_INT] \
+ (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
--- 2184,2192 ----
: 0)
#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
! (TARGET_SH5 \
! && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
! || (MODE) == DCmode) \
&& ((CUM).arg_count[(int) SH_ARG_INT] \
+ (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
*************** while (0)
*** 2462,2468 ****
/* The `Csy' constraint is a label or a symbol. */
#define EXTRA_CONSTRAINT_Csy(OP) \
! (NON_PIC_REFERENCE_P (OP))
/* A zero in any shape or form. */
#define EXTRA_CONSTRAINT_Z(OP) \
--- 2490,2496 ----
/* The `Csy' constraint is a label or a symbol. */
#define EXTRA_CONSTRAINT_Csy(OP) \
! (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
/* A zero in any shape or form. */
#define EXTRA_CONSTRAINT_Z(OP) \
*************** while (0)
*** 2889,2898 ****
/* We can't directly access anything that contains a symbol,
nor can we indirect via the constant pool. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
! (! nonpic_symbol_mentioned_p (X) \
! && (GET_CODE (X) != SYMBOL_REF \
! || ! CONSTANT_POOL_ADDRESS_P (X) \
! || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
#define SYMBOLIC_CONST_P(X) \
((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
--- 2917,2927 ----
/* We can't directly access anything that contains a symbol,
nor can we indirect via the constant pool. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
! ((! nonpic_symbol_mentioned_p (X) \
! && (GET_CODE (X) != SYMBOL_REF \
! || ! CONSTANT_POOL_ADDRESS_P (X) \
! || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
! || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
#define SYMBOLIC_CONST_P(X) \
((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
Index: config/sh/sh.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.md,v
retrieving revision 1.149
diff -p -r1.149 sh.md
*** config/sh/sh.md 16 Jun 2003 16:23:30 -0000 1.149
--- config/sh/sh.md 17 Jun 2003 16:28:55 -0000
***************
*** 6637,6655 ****
}
")
- ;; When generating PIC, we must match label_refs especially, because
- ;; they do not satisfy LEGITIMATE_PIC_OPERAND_P(), and we don't want
- ;; them to do, because they can't be loaded directly into
- ;; non-branch-target registers.
- (define_insn "*pt"
- [(set (match_operand:DI 0 "target_reg_operand" "=b")
- (match_operand:DI 1 "" "Csy"))]
- "TARGET_SHMEDIA && flag_pic
- && EXTRA_CONSTRAINT_Csy (operands[1])"
- "pt %1, %0"
- [(set_attr "type" "pt_media")
- (set_attr "length" "*")])
-
(define_insn "*ptb"
[(set (match_operand:DI 0 "target_reg_operand" "=b")
(const:DI (unspec:DI [(match_operand:DI 1 "" "Csy")]
--- 6637,6642 ----
*************** mov.l\\t1f,r0\\n\\
*** 7237,7242 ****
--- 7224,7235 ----
"blink %0, r63"
[(set_attr "type" "jump_media")])
+ (define_insn "return_media_rte"
+ [(return)]
+ "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
+ "rte"
+ [(set_attr "type" "jump_media")])
+
(define_expand "return_media"
[(return)]
"TARGET_SHMEDIA && reload_completed"
*************** mov.l\\t1f,r0\\n\\
*** 7245,7250 ****
--- 7238,7248 ----
int tr_regno = sh_media_register_for_return ();
rtx tr;
+ if (current_function_interrupt)
+ {
+ emit_jump_insn (gen_return_media_rte ());
+ DONE;
+ }
if (tr_regno < 0)
{
rtx r18 = gen_rtx_REG (DImode, PR_MEDIA_REG);
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