3.4 PATCH: Enable mips2 default for IRIX 6 O32

[Rainer Orth]

Eric Christopher writes:

> 
> > It turns out that while the IRIX 6 O32 as understands the break
> > instruction, the first operand (breakcode1) is mandatory, while optional
> > for gas.  See
> > 
> > 	http://techpubs.sgi.com/library/tpl/cgi-bin/getdoc.cgi/0650/bks/SGI_Developer/books/MProAsLg_PG/sgi_html/ch05.html#Z81460
> > 
> > This is a bug in the trap define_insn, which should be fixed.
> > 
> 
> Please file this in bugzilla unless you plan on fixing it shortly then
> :)

I think the fix is trivial.  I've verified that unadorned break with gas
produces the same opcode as break 0 with the IRIX 6 O32 assembler.


Tue Jun 17 13:36:35 2003  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>

	* config/mips/mips.md (trap): Use break 0 when !TARGET_GAS.

Index: gcc/config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.175
diff -u -p -r1.175 mips.md
--- gcc/config/mips/mips.md	17 Jun 2003 06:44:46 -0000	1.175
+++ gcc/config/mips/mips.md	17 Jun 2003 14:02:30 -0000
@@ -640,7 +640,8 @@
 {
   if (ISA_HAS_COND_TRAP)
     return \"teq\\t$0,$0\";
-  else if (TARGET_MIPS16)
+  /* The IRIX 6 O32 assembler requires the first break operand.  */
+  else if (TARGET_MIPS16 || ! TARGET_GAS)
     return \"break 0\";
   else
     return \"break\";

Is bootstrapping on mips-sgi-irix6.5o32 with this patch and running one of
the previously (with mips1 default) failing testcases enough for
verification? 

> > O32 ABI default ISA, mips1.  The following patch fixes this by undefining
> > MIPS_CPU_STRING_DEFAULT.
> > Ok for mainline?
> 
> Please define to r6000 instead.

I'll go for mips2, as Richard Sandiford suggested in private mail.  I don't
think any SGI box ever had an R6000 CPU, so this would be confusing.

I'll repost once bootstrap has finished successfully.

	Rainer

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Rainer Orth, Faculty of Technology, Bielefeld University