fix target/11089

[Richard Henderson]

We abort in instantiate_virtual_regs simply because this is
the first time we try to recognize insns.  In this case it
was incorrect from the moment we generated it.

Fixed thus.


r~


        PR target/11089
        * config/i386/i386.md (sse_movaps): Use an expander to force
        one operand to be a register.
        (sse_movups): Likewise.

Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.404.2.17
diff -c -p -d -r1.404.2.17 i386.md
*** config/i386/i386.md	9 Jun 2003 21:37:51 -0000	1.404.2.17
--- config/i386/i386.md	13 Jun 2003 06:03:51 -0000
***************
*** 18308,18314 ****
  
  ;; These two patterns are useful for specifying exactly whether to use
  ;; movaps or movups
! (define_insn "sse_movaps"
    [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
  	(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
  		     UNSPEC_MOVA))]
--- 18308,18329 ----
  
  ;; These two patterns are useful for specifying exactly whether to use
  ;; movaps or movups
! (define_expand "sse_movaps"
!   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
! 	(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
! 		     UNSPEC_MOVA))]
!   "TARGET_SSE"
! {
!   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
!     {
!       rtx tmp = gen_reg_rtx (V4SFmode);
!       emit_insn (gen_sse_movaps (tmp, operands[1]));
!       emit_move_insn (operands[0], tmp);
!       DONE;
!     }
! })
! 
! (define_insn "*sse_movaps_1"
    [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
  	(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
  		     UNSPEC_MOVA))]
***************
*** 18318,18324 ****
    [(set_attr "type" "ssemov,ssemov")
     (set_attr "mode" "V4SF")])
  
! (define_insn "sse_movups"
    [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
  	(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
  		     UNSPEC_MOVU))]
--- 18333,18354 ----
    [(set_attr "type" "ssemov,ssemov")
     (set_attr "mode" "V4SF")])
  
! (define_expand "sse_movups"
!   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
! 	(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
! 		     UNSPEC_MOVU))]
!   "TARGET_SSE"
! {
!   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
!     {
!       rtx tmp = gen_reg_rtx (V4SFmode);
!       emit_insn (gen_sse_movups (tmp, operands[1]));
!       emit_move_insn (operands[0], tmp);
!       DONE;
!     }
! })
! 
! (define_insn "*sse_movups_1"
    [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
  	(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
  		     UNSPEC_MOVU))]
***************
*** 18327,18333 ****
    "movups\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssecvt,ssecvt")
     (set_attr "mode" "V4SF")])
- 
  
  ;; SSE Strange Moves.
  
--- 18357,18362 ----
Index: testsuite/gcc.dg/i386-sse-4.c
===================================================================
RCS file: testsuite/gcc.dg/i386-sse-4.c
diff -N testsuite/gcc.dg/i386-sse-4.c
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- testsuite/gcc.dg/i386-sse-4.c	13 Jun 2003 06:03:54 -0000
***************
*** 0 ****
--- 1,27 ----
+ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+ /* { dg-options "-O0 -msse" } */
+ 
+ typedef void __vr __attribute__ ((__mode__ (__V4SF__)));
+ 
+ struct vector
+ {
+   union
+   {
+     __vr v;
+     float f[4];
+   };
+ };
+ 
+ void
+ doit ()
+ {
+   float f[4];
+   struct vector v;
+ 
+   f[0] = 0;
+   f[1] = 1;
+   f[2] = 2;
+   f[3] = 3;
+ 
+   v.v = __builtin_ia32_loadups (f);
+ }