Patch to add rm9000 support
Richard Sandiford
rsandifo@redhat.com
Tue Jul 15 08:46:00 GMT 2003
Approved by Eric & applied.
Richard
(Although the ChangeLog bears a striking similarity to the rm7k one,
the contents are different, honest.)
* config/mips/mips.h (PROCESSOR_R9000): New processor_type.
(TARGET_MIPS9000, TUNE_MIPS9000): New macros.
(GENERATE_MULT3_SI): True for TARGET_MIPS9000.
* config/mips/mips.c (mips_cpu_info_table): Add rm9000 entry.
(mips_rtx_costs): Adjust integer multiplication costs for the rm9000.
(mips_issue_rate): Handle PROCESSOR_R9000.
(mips_use_dfa_pipeline_interface): Likewise.
* config/mips/9000.md: New file.
* config/mips/mips.md: Include it.
(define_attr cpu): Add r9000.
(mulsi3_mult3): Use "mul" for rm9000 code.
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.278
diff -c -d -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.278 mips.h
*** config/mips/mips.h 15 Jul 2003 08:34:50 -0000 1.278
--- config/mips/mips.h 15 Jul 2003 08:39:03 -0000
*************** enum processor_type {
*** 67,72 ****
--- 67,73 ----
PROCESSOR_R5500,
PROCESSOR_R7000,
PROCESSOR_R8000,
+ PROCESSOR_R9000,
PROCESSOR_SB1,
PROCESSOR_SR71000
};
*************** #define TARGET_MIPS5KC (mip
*** 331,336 ****
--- 332,338 ----
#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
+ #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
*************** #define TUNE_MIPS5400 (mip
*** 343,348 ****
--- 345,351 ----
#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
+ #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
#define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
*************** #define GENERATE_MULT3_SI ((TARGET
*** 766,771 ****
--- 769,775 ----
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_MIPS7000 \
+ || TARGET_MIPS9000 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.293
diff -c -d -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.293 mips.c
*** config/mips/mips.c 15 Jul 2003 08:34:53 -0000 1.293
--- config/mips/mips.c 15 Jul 2003 08:39:05 -0000
*************** const struct mips_cpu_info mips_cpu_info
*** 808,813 ****
--- 808,814 ----
{ "vr5400", PROCESSOR_R5400, 4 },
{ "vr5500", PROCESSOR_R5500, 4 },
{ "rm7000", PROCESSOR_R7000, 4 },
+ { "rm9000", PROCESSOR_R9000, 4 },
/* MIPS32 */
{ "4kc", PROCESSOR_4KC, 32 },
*************** mips_rtx_costs (x, code, outer_code, tot
*** 2664,2669 ****
--- 2665,2672 ----
*total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
else if (TUNE_MIPS7000)
*total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
+ else if (TUNE_MIPS9000)
+ *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (17);
else if (TUNE_MIPS5000)
*************** mips_issue_rate ()
*** 10265,10270 ****
--- 10268,10274 ----
case PROCESSOR_R5400: return 2;
case PROCESSOR_R5500: return 2;
case PROCESSOR_R7000: return 2;
+ case PROCESSOR_R9000: return 2;
default:
return 1;
*************** mips_use_dfa_pipeline_interface ()
*** 10285,10290 ****
--- 10289,10295 ----
case PROCESSOR_R5400:
case PROCESSOR_R5500:
case PROCESSOR_R7000:
+ case PROCESSOR_R9000:
case PROCESSOR_SR71000:
return true;
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.183
diff -c -d -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.183 mips.md
*** config/mips/mips.md 15 Jul 2003 08:34:54 -0000 1.183
--- config/mips/mips.md 15 Jul 2003 08:39:07 -0000
*************** (define_attr "length" ""
*** 195,201 ****
;; ??? Fix everything that tests this attribute.
(define_attr "cpu"
! "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,sb1,sr71000"
(const (symbol_ref "mips_cpu_attr")))
;; The type of hardware hazard associated with this instruction.
--- 195,201 ----
;; ??? Fix everything that tests this attribute.
(define_attr "cpu"
! "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
(const (symbol_ref "mips_cpu_attr")))
;; The type of hardware hazard associated with this instruction.
*************** (define_function_unit "imuldiv" 1 0
*** 624,629 ****
--- 624,630 ----
(include "5400.md")
(include "5500.md")
(include "7000.md")
+ (include "9000.md")
(include "sr71k.md")
*************** (define_insn "mulsi3_mult3"
*** 1498,1503 ****
--- 1499,1505 ----
|| TARGET_MIPS5400
|| TARGET_MIPS5500
|| TARGET_MIPS7000
+ || TARGET_MIPS9000
|| ISA_MIPS32
|| ISA_MIPS32R2
|| ISA_MIPS64)
*** /dev/null Thu Apr 11 15:25:15 2002
--- config/mips/9000.md Tue Jul 15 09:34:51 2003
***************
*** 0 ****
--- 1,154 ----
+ ;; DFA-based pipeline description for the RM9000.
+ ;; Copyright (C) 2003 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+ (define_automaton "rm9k_main, rm9k_imul, rm9k_fdiv")
+
+ ;; These units are for insns that can issue in either pipe. We don't
+ ;; want to use constructs like "rm9k_m | rm9k_f_int" since that would
+ ;; needlessly make an insn prefer the M pipe.
+ (define_cpu_unit "rm9k_any1" "rm9k_main")
+ (define_cpu_unit "rm9k_any2" "rm9k_main")
+
+ ;; F and M pipe units, for instructions that must be issued by a
+ ;; particular pipe. Split the F pipe into two units so that integer
+ ;; instructions can issue while the FPU is busy. We don't need to
+ ;; split M because it is only ever reserved for a single cycle.
+ (define_cpu_unit "rm9k_m" "rm9k_main")
+ (define_cpu_unit "rm9k_f_int" "rm9k_main")
+ (define_cpu_unit "rm9k_f_float" "rm9k_main")
+
+ (exclusion_set "rm9k_f_int" "rm9k_f_float")
+
+ ;; Multiply/divide units.
+ (define_cpu_unit "rm9k_imul" "rm9k_imul")
+ (define_cpu_unit "rm9k_fdiv" "rm9k_fdiv")
+
+ (define_insn_reservation "rm9k_load" 3
+ (and (eq_attr "cpu" "r9000")
+ (eq_attr "type" "load"))
+ "rm9k_m")
+
+ (define_insn_reservation "rm9k_store" 1
+ (and (eq_attr "cpu" "r9000")
+ (eq_attr "type" "store"))
+ "rm9k_m")
+
+ (define_insn_reservation "rm9k_int" 1
+ (and (eq_attr "cpu" "r9000")
+ (eq_attr "type" "move,arith,darith,const,icmp,nop"))
+ "rm9k_any1 | rm9k_any2")
+
+ (define_insn_reservation "rm9k_int_cmove" 2
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "condmove")
+ (eq_attr "mode" "SI,DI")))
+ "rm9k_any1 | rm9k_any2")
+
+ ;; This applies to both 'mul' and 'mult'.
+ (define_insn_reservation "rm9k_mulsi" 3
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "!DI")))
+ "rm9k_f_int")
+
+ (define_insn_reservation "rm9k_muldi" 7
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "DI")))
+ "rm9k_f_int + rm9k_imul * 7")
+
+ (define_insn_reservation "rm9k_divsi" 38
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "!DI")))
+ "rm9k_f_int + rm9k_imul * 38")
+
+ (define_insn_reservation "rm9k_divdi" 70
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "rm9k_f_int + rm9k_imul * 70")
+
+ (define_insn_reservation "rm9k_mfhilo" 1
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "hilo")
+ (not (match_operand 0 "hilo_operand" ""))))
+ "rm9k_f_int")
+
+ (define_insn_reservation "rm9k_mthilo" 5
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "hilo")
+ (match_operand 0 "hilo_operand" "")))
+ "rm9k_f_int")
+
+ (define_insn_reservation "rm9k_xfer" 2
+ (and (eq_attr "cpu" "r9000")
+ (eq_attr "type" "xfer"))
+ "rm9k_m")
+
+ (define_insn_reservation "rm9k_fquick" 2
+ (and (eq_attr "cpu" "r9000")
+ (eq_attr "type" "fabs,fneg,fcmp"))
+ "rm9k_f_float")
+
+ (define_insn_reservation "rm9k_fcmove" 2
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "condmove")
+ (eq_attr "mode" "SF,DF")))
+ "rm9k_m")
+
+ (define_insn_reservation "rm9k_fadd" 6
+ (and (eq_attr "cpu" "r9000")
+ (eq_attr "type" "fadd,fcvt"))
+ "rm9k_f_float")
+
+ (define_insn_reservation "rm9k_fmuls" 6
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "rm9k_f_float")
+
+ (define_insn_reservation "rm9k_fmuld" 9
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "rm9k_f_float * 3")
+
+ (define_insn_reservation "rm9k_fdivs" 22
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "SF")))
+ "rm9k_f_float + rm9k_fdiv * 22")
+
+ (define_insn_reservation "rm9k_fdivd" 37
+ (and (eq_attr "cpu" "r9000")
+ (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "DF")))
+ "rm9k_f_float + rm9k_fdiv * 37")
+
+ (define_insn_reservation "rm9k_branch" 2
+ (and (eq_attr "cpu" "r9000")
+ (eq_attr "type" "branch,jump,call"))
+ "rm9k_any1 | rm9k_any2")
+
+ (define_insn_reservation "rm9k_unknown" 1
+ (and (eq_attr "cpu" "r9000")
+ (eq_attr "type" "unknown,multi"))
+ "rm9k_m + rm9k_f_int + rm9k_any1 + rm9k_any2")
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